AX5031 Datasheet

0N Semiconductor® www.0nseml.com Q
© Semiconductor Components Industries, LLC, 2016
April, 2016 Rev. 3
1Publication Order Number:
AX5031/D
AX5031
Advanced Multi-channel
Single Chip UHF Transmitter
OVERVIEW
The AX5031 is a true single chip lowpower CMOS transmitter
primarily for use in SRD bands. The onchip transmitter consists of a
fully integrated RF frontend with modulator, and demodulator. Base
band data processing is implemented in an advanced and flexible
communication controller that enables user friendly communication
via the SPI interface.
AX5031 can be operated from a 2.2 V to 3.6 V power supply over a
temperature range of 40°C to 85°C, it consumes 11 45 mA for
transmitting, depending on the output power.
Features
Advanced Multichannel Single Chip UHF Transmitter
Configurable for Usage in 400470 MHz and 800940 MHz
ISM Bands
5 dBm to +15 dBm Programmable Output
13 mA @ 0 dBm, 868 MHz
22 mA @ 10 dBm, 868 MHz
44 mA @ 15 dBm, 868 MHz
Wide Variety of Shaped Modulations Supported (ASK, PSK,
OQPSK, MSK, FSK, GFSK, 4FSK)
Data Rates from 1 to 350 kbps (FSK, MSK, GFSK,
4FSK), 1 to 2000 kbps (ASK), 10 to 2000 kbps (PSK)
Ultra Fast Settling RF Frequency Synthesizer for
Lowpower Consumption
802.15.4 Compatible
RF Carrier Frequency and FSK Deviation
Programmable in 1 Hz Steps
Fully Integrated RF Frequency Synthesizer with VCO
Autoranging and Bandwidth Boost Modes for Fast
Locking
Few External Components
On Chip Communication Controller and Flexible
Digital Modulator
Channel Hopping 2000 hops/s
Crystal Oscillator with Programmable
Transconductance and Programmable Internal Tuning
Capacitors for Low Cost Crystals
SPI Microcontroller Interface
QFN20 Package
Supply Voltage Range 2.2 V 3.6 V
Internal Poweronreset
32 Byte Data FIFO
Programmable Cyclic Redundancy Check
(CRCCCITT, CRC16, CRC32)
Optional Spectral Shaping Using a Self Synchronizing
Shift Register
Brownout Detection
Differential Antenna Pins
Dual Frequency Registers
Internally Generated Coding for Forward Viterbi Error
Correction
Software Compatible to AX5051
Applications
Telemetry
Sensor Readout, Thermostats
AMR
Toys
Wireless Audio
Wireless Networks
Wireless MBus
Access Control
Remote Keyless Entry
Remote Controls
Active RFID
Compatible with FCC Part 15.247, FCC Part 15.249,
EN 300 220 Wideband, Wireless MBus S/TMode,
Konnex RF, ARIB T67
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ORDERING INFORMATION
Device Type Qty
AX50311TA05 Tape & Reel 500
AX50311TW30 Tape & Reel 3,000
1
QFN20 4x4, 0.5P
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BLOCK DIAGRAM
Figure 1. Functional Block Diagram of the AX5031
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PIN FUNCTION DESCRIPTIONS
Table 1. PIN LIST
Symbol Pin(s) Type Description
VDD 1 P Power supply, must be supplied with regulated voltage VREG
ANTP 2 A Antenna output
ANTN 3 A Antenna output
VDD 4 P Power supply, must be supplied with regulated voltage VREG
NC 5 N Not connected
NC 6 N Not connected
SYSCLK 7 I/O Default functionality: Crystal oscillator (or divided) clock output
Can be programmed to be used as a general purpose I/O pin.
SEL 8 I Serial peripheral interface select
CLK 9 I Serial peripheral interface clock
MISO 10 O Serial peripheral interface data output
NC 11 NNot connected
MOSI 12 I Serial peripheral interface data input
NC 13 N Not connected
IRQ 14 I/O Default functionality: Interrupt
Can be programmed to be used as a general purpose I/O pin.
VDD_IO 15 P Unregulated power supply
NC 16 N Not connected
VREG 17 P Regulated output voltage
VDD pins must be connected to this supply voltage.
A 1 mF low ESR capacitor to GND must be connected to this pin.
NC 18 P Not to be connected
CLK16P 19 A Crystal oscillator input/output
CLK16N 20 A Crystal oscillator input/output
GND Center pad PGround on center pad of QFN
A = analog input
I = digital input signal
O = digital output signal
I/O = digital input/output signal
N = not to be connected
P = power or ground
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible and 5 V
tolerant.
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Pinout Drawing
Figure 2. Pinout Drawing (Top View)
1
2
3
4
5
VDD
ANTP
VDD
NC
ANTN
MOSI
NC
11
15
14
13
12
IRQ
VDD_IO
NC
910876
19 16
18 1720
CLK16N
VREG
CLK16P
NC
NC
AX5031
GND connection is done via the exposed centre pad of the QFN package.
NC
SYSCLK
SEL
CLK
MISO
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SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol Description Condition Min Max Units
VDD_IO Supply voltage 0.5 5.5 V
IDD Supply current 100 mA
Ptot Total power consumption 800 mW
II1 DC current into any pin except ANTP, ANTN 10 10 mA
II2 DC current into pins ANTP, ANTN 100 100 mA
IOOutput Current 40 mA
Via Input voltage ANTP, ANTN pins 0.5 5.5 V
Input voltage digital pins 0.5 5.5 V
Ves Electrostatic handling HBM 2000 2000 V
Tamb Operating temperature 40 85 °C
Tstg Storage temperature 65 150 °C
TjJunction Temperature 150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
Table 3. SUPPLIES
Symbol Description Condition Min Typ Max Units
TAMB Operational ambient temperature 40 27 85 °C
VDD_IO I/O and voltage regulator supply voltage 2.2 3.0 3.6 V
VREG Internally regulated supply voltage Powerdown mode PWRMODE = 0x00 1.7 V
All other power modes 2.1 2.5 2.8
IPDOWN Powerdown current PWRMODE = 0x00 0.25 mA
ITX Current consumption TX for maximum
power with default matching network at
3.3 V VDD_IO. (Note 1)
868 MHz, 15 dBm 44 mA
433 MHz, 15 dBm 45
TXVARVDD Variation of output power over voltage VDD_IO > 2.5 V, (Note 1) ±0.5 dB
TXVARTEMP Variation of output power over
temperature
VDD_IO > 2.5 V, (Note 1) ±0.5 dB
1. The PA voltage is regulated to 2.5 V. For VDD_IO levels in the range of 2.2 V to 2.5 V the output power drops by typically 1 dBm.
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Note on current consumption in TX mode
To achieve best output power the matching network has to
be optimized for the desired output power and frequency. As
a rule of thumb a good matching network produces about
50% efficiency with the AX5031 power amplifier although
over 90% are theoretically possible. A typical matching
network has between 1 dB and 2 dB loss (Ploss).
The current consumption can be calculated as
ITX[mA] +1
PAefficiency 10ǒPout[dBm])Ploss[dB]
10 ǓB2.5V )Ioffse
t
Ioffset is about 12 mA for the VCO at 400470 MHz and
11 mA for 800940 MHz. The following table shows
calculated current consumptions versus output power for
Ploss = 1 dB, PAefficiency = 0.5 and Ioffset= 11 mA at 868 MHz.
Table 4.
Pout [dBm] I [mA]
0 13.0
1 13.2
2 13.6
3 14.0
4 14.5
5 15.1
6 16.0
7 17.0
8 18.3
9 20.0
10 22.0
11 24.6
12 27.96
13 32.1
14 37.3
15 43.8
The AX5031 power amplifier runs from the regulated
VDD supply and not directly from the battery. This has the
advantage that the current and output power do not vary
much over supply voltage and temperature from 2.55 V to
3.6 V supply voltage. Between 2.55 V and 2.2 V a drop of
about 1 dB in output power occurs.
Table 5. LOGIC
Symbol Description Condition Min Typ Max Units
Digital Inputs
VT+ Schmitt trigger low to high threshold point 1.9 V
VTSchmitt trigger high to low threshold point 1.2 V
VIL Input voltage, low 0.8 V
VIH Input voltage, high 2.0 V
ILInput leakage current 10 10 mA
Digital Outputs
IOH Output Current, high VOH = 2.4 V 4 mA
IOL Output Current, low VOL = 0.4 V 4 mA
IOZ Tristate output leakage current 10 10 mA
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AC Characteristics
Table 6. CRYSTAL OSCILLATOR
Symbol Description Condition Min Typ Max Units
fXTAL Crystal frequency Note 1, 3 15.5 16 25 MHz
gmosc Transconductance oscillator XTALOSCGM = 0000 1mS
XTALOSCGM = 0001 2
XTALOSCGM = 0010
default
3
XTALOSCGM = 0011 4
XTALOSCGM = 0100 5
XTALOSCGM = 0101 6
XTALOSCGM = 0110 6.5
XTALOSCGM = 0111 7
XTALOSCGM = 1000 7.5
XTALOSCGM = 1001 8
XTALOSCGM = 1010 8.5
XTALOSCGM = 1011 9
XTALOSCGM = 1100 9.5
XTALOSCGM = 1101 10
XTALOSCGM = 1110 10.5
XTALOSCGM = 1111 11
Cosc Programmable tuning capacitors at pins
CLK16N and CLK16P
XTALCAP = 000000 default 2pF
XTALCAP = 111111 33
Cosclsb Programmable tuning capacitors,
increment per LSB of XTALCAP
0.5 pF
Aosc Oscillator amplitude at pin CLK16P Note 2 0.5 V
RINosc Input DC impedance 10 kW
1. Tolerances and startup times depend on the crystal used.
2. If an external clock is used, it should be input via an AC coupling at pin CLK16P with the oscillator powered up and XTALCAP = 000000
3. Lower frequencies than 15.5 MHz or higher frequencies than 25 MHz can be used. However, not all typical RF frequencies can be generated.
Table 7. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)
Symbol Description Condition Min Typ Max Units
fREF Reference frequency Note 1 16, 24 MHz
frange_hi Frequency range BANDSEL = 0 800 940 MHz
frange_low BANDSEL = 1 400 470
fRESO Frequency resolution 1 Hz
BW1Synthesizer loop
bandwidth
Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 010
100 kHz
BW2Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 001
50
BW3Loop filter configuration: FLT = 11
Charge pump current: PLLCPI = 010
200
BW4Loop filter configuration: FLT = 10
Charge pump current: PLLCPI = 010
500
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Table 7. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)
Symbol UnitsMaxTypMinConditionDescription
Tset1 Synthesizer settling time
for 1 MHz step
Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 010
15 ms
Tset2 Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 001
30
Tset3 Loop filter configuration: FLT = 11
Charge pump current: PLLCPI = 010
7
Tset4 Loop filter configuration: FLT = 10
Charge pump current: PLLCPI = 010
3
Tstart1 Synthesizer startup time
if crystal oscillator and
reference are running
Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 010
25 ms
Tstart2 Loop filter configuration: FLT = 01
Charge pump current: PLLCPI = 001
50
Tstart3 Loop filter configuration: FLT = 11
Charge pump current: PLLCPI = 010
12
Tstart4 Loop filter configuration: FLT = 10
Charge pump current: PLLCPI = 010
5
PN8681Synthesizer phase noise
Loop filter configuration:
FLT = 01
Charge pump current:
PLLCPI = 010
868 MHz, 50 kHz from carrier 85 dBc/Hz
868 MHz, 100 kHz from carrier 90
868 MHz, 300 kHz from carrier 100
868 MHz, 2 MHz from carrier 110
PN4331433 MHz, 50 kHz from carrier 90
433 MHz, 100 kHz from carrier 95
433 MHz, 300 kHz from carrier 105
433 MHz, 2 MHz from carrier 115
PN8682Synthesizer phase noise
Loop filter configuration:
FLT = 01
Charge pump current:
PLLCPI = 001
868 MHz, 50 kHz from carrier 80 dBc/Hz
868 MHz, 100 kHz from carrier 90
868 MHz, 300 kHz from carrier 105
868 MHz, 2 MHz from carrier 115
PN4332433 MHz, 50 kHz from carrier 90
433 MHz, 100 kHz from carrier 95
433 MHz, 300 kHz from carrier 110
433 MHz, 2 MHz from carrier 122
1. ASK, PSK and 1200 kbps FSK with 16 MHz crystal, 200350 kbps FSK with 24 MHz crystal.
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Table 8. TRANSMITTER
Symbol Description Condition Min Typ Max Units
SBR Signal bit rate ASK 1 2000 kbps
FSK, (Note 2) 1 350
PSK 10 2000
802.15.4 (DSSS)
ASK and PSK
1 40
802.15.4 (DSSS)
FSK
1 16
PTX868 Transmitter power @ 868 MHz TXRNG = 0000 45 dBm
TXRNG = 0001 5
TXRNG = 0010 0.4
TXRNG = 0011 4
TXRNG = 0100 6.2
TXRNG = 0101 8
TXRNG = 0110 9.3
TXRNG = 0111 10.3
TXRNG = 1000 11.2
TXRNG = 1001 11.9
TXRNG = 1010 12.5
TXRNG = 1011 13
TXRNG = 1100 13.5
TXRNG = 1101 13.8
TXRNG = 1110 14
TXRNG = 1111 14.5
PTX433 Transmitter power @ 433 MHz TXRNG = 1111 15.5 dBm
PTX868harm2 Emission @ 2nd harmonic (Note 1) 50 dBc
PTX868harm3 Emission @ 3rd harmonic 55
1. Additional lowpass filtering was applied to the antenna interface, see section Application Information.
2. 1 200 kbps with 16 MHz crystal, 200 350 kbps with 24 MHz crystal
Table 9. SPI TIMING
Symbol Description Condition Min Typ Max Units
Tss SEL falling edge to CLK rising edge 10 ns
Tsh CLK falling edge to SEL rising edge 10 ns
Tssd SEL falling edge to MISO driving 0 10 ns
Tssz SEL rising edge to MISO highZ 0 10 ns
Ts MOSI setup time 10 ns
Th MOSI hold time 10 ns
Tco CLK falling edge to MISO output 10 ns
Tck CLK period Note 1 50 ns
Tcl CLK low duration 40 ns
Tch CLK high duration 40 ns
1. For SPI access during powerdown mode the period should be relaxed to 100 ns.
For a figure showing the SPI timing parameters see section Serial Peripheral Interface (SPI).
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CIRCUIT DESCRIPTION
The AX5031 is a true single chip lowpower CMOS
transmitter primarily for use in SRD bands. The onchip
transmitter consists of a fully integrated RF frontend with
modulator, and demodulator. Base band data processing is
implemented in an advanced and flexible communication
controller that enables user friendly communication via the
SPI interface.
AX5031 can be operated from a 2.2 V to 3.6 V power
supply over a temperature range of 40°C to 85°C, it
consumes 11 45 mA for transmitting, depending on the
output power.
The AX5031 features make it an ideal interface for
integration into various battery powered SRD solutions such
as ticketing or as transmitter for telemetric applications e.g.
in sensors. As primary application, the transmitter is
intended for UHF radio equipment in accordance with the
European Telecommunication Standard Institute (ETSI)
specification EN 300 2201 and the US Federal
Communications Commission (FCC) standard CFR47, part
15. The use of AX5031 in accordance to FCC Par 15.247,
allows for improved range in the 915 MHz band.
Additionally AX5031 is compatible with the low frequency
standards of 802.15.4 (ZigBee).
The AX5031 receives data via the SPI port in frames. This
standard operation mode is called Frame Mode. Pre and post
ambles as well as checksums can be generated
automatically. Interrupts control the data flow between a
controller and the AX5031.
The AX5031 behaves as a SPI slave interface.
Configuration of the AX5031 is also done via the SPI
interface.
AX5031 supports any data rate from 1 kbps to 350 kbps
for FSK and MSK, from 1 kbps to 2000 kbps for ASK and
from 10 kbps to 2000 kbps for PSK. To achieve optimum
performance for specific data rates and modulation schemes
several register settings to configure the AX5031 are
necessary, they are outlined in the following, for details see
the AX5031 Programming Manual.
Spreading is possible on all data rates and modulation
schemes. The net transfer rate is reduced by a factor of 15 in
this case. For ZigBee either 600 or 300 kbps modes have to
be chosen.
Voltage Regulator
The AX5031 uses an onchip voltage regulator to create
a stable supply voltage for the internal circuitry at pin VREG
from the primary supply VDD_IO. All VDD pins of the
device must be connected to VREG. The antenna pins
ANTP and ANTN must be DC biased to VREG. The I/O
level of the digital pins is VDD_IO.
The voltage regulator requires a 1 mF low ESR capacitor
at pin VREG.
In powerdown mode the voltage regulator typically
outputs 1.7 V at VREG, if it is poweredup its output rises
to typically 2.5 V. At device powerup the regulator is in
powerdown mode.
The voltage regulator must be poweredup before
transmit operations can be initiated. This is handled
automatically when programming the device modes via the
PWRMODE register.
Register VREG contains status bits that can be read to
check if the regulated voltage is above 1.3 V or 2.3 V, sticky
versions of the bits are provided that can be used to detect
low power events (brownout detection).
Crystal Oscillator
The onchip crystal oscillator allows the use of an
inexpensive quartz crystal as the RF generation subsystem’s
timing reference. Although a wider range of crystal
frequencies can be handled by the crystal oscillator circuit,
it is recommended to use 16 MHz as reference frequency for
ASK and PSK modulations independent of the data rate. For
FSK it is recommended to use a 16 MHz crystal for data rates
below 200 kbps and 24 MHz for data rates above 200 kbps.
The oscillator circuit is enabled by programming the
PWRMODE register. At powerup it is not enabled.
To adjust the circuit’s characteristics to the quartz crystal
being used without using additional external components,
both the transconductance and the tuning capacitance of the
crystal oscillator can be programmed.
The transconductance is programmed via register bits
XTALOSCGM[3:0] in register XTALOSC.
The integrated programmable tuning capacitor bank
makes it possible to connect the oscillator directly to pins
CLK16N and CLK16P without the need for external
capacitors. It is programmed using bits XTALCAP[5:0] in
register XTALCAP.
SYSCLK Output
The SYSCLK pin outputs the reference clock signal
divided by a programmable integer. Divisions from 1 to
2048 are possible. For divider ratios > 1 the duty cycle is
50%. Bits SYSCLK[3:0] in the PINCFG1 register set the
divider ratio. The SYSCLK output can be disabled.
Poweronreset (POR)
AX5031 has an integrated poweronreset block. No
external POR circuit or signal is required.
After POR the AX5031 can be reset by SPI accesses, this
is achieved by toggling the bit RST in the PWRMODE
register.
After POR or reset all registers are set to their default
values.
RF Frequency Generation Subsystem
The RF frequency generation subsystem consists of a
fully integrated synthesizer, which multiplies the reference
frequency from the crystal oscillator to get the desired RF
frequency. The advanced architecture of the synthesizer
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enables frequency resolutions of 1 Hz, as well as fast settling
times of 5 – 50 ms depending on the settings (see section:
AC Characteristics). Fast settling times mean fast startup,
which enables lowpower system design.
The frequency must be programmed to the desired carrier
frequency.
The synthesizer loop bandwidth can be programmed, this
serves three purposes:
1. Startup time optimization, startup is faster for
higher synthesizer loop bandwidths.
2. TX spectrum optimization, phasenoise at
300 kHz to 1 MHz distance from the carrier
improves with lower synthesizer loop bandwidths.
3. Adaptation of the bandwidth to the datarate. For
transmission of FSK and MSK it is required that
the synthesizer bandwidth must be in the order of
the datarate.
VCO
An onchip VCO converts the control voltage generated
by the charge pump and loop filter into an output frequency.
The frequency can be programmed in 1 Hz steps in the
FREQ or FREQB registers. To chose FREQB setting rather
than FREQ, the bit FREQSEL in register PLLLOOP must
be set. For operation in the 433 MHz band, the BANDSEL
bit in the PLLLOOP register must be programmed.
VCO AutoRanging
The AX5031 has an integrated autoranging function,
which allows to set the correct VCO range for specific
frequency generation subsystem settings automatically.
Typically it has to be executed after powerup. The function
is initiated by setting the RNG_START bit in the
PLLRANGING register. The bit is readable and a 0 indicates
the end of the ranging process. The RNGERR bit indicates
the correct execution of the autoranging.
Loop Filter and Charge Pump
The AX5031 internal loop filter configuration together
with the charge pump current sets the synthesizer loop band
width. The loopfilter has three configurations that can be
programmed via the register bits FLT[1:0] in register
PLLLOOP, the charge pump current can be programmed
using register bits PLLCPI[1:0] also in register PLLLOOP.
Synthesizer bandwidths are typically 50 – 500 kHz
depending on the PLLLOOP settings, for details see the
section: AC Characteristics.
Registers
Table 10. REGISTERS
Register Bits Purpose
PLLLOOP FREQSEL Switches between carrier frequencies defined by FREQ and FREQB.
Using this feature allows to avoid glitches in the PLL output frequency caused by serially
changing the 4 bytes required to set a carrier frequency.
FLT[1:0] Synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster
settling time, bandwidth increases of factor 2 and 5 are possible.
PLLCPI[2:0] Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and
improve the phasenoise) for low datarate transmissions.
BANDSEL Switches between 868 MHz / 915 MHz and 433 MHz bands
FREQ Programming of the carrier frequency
FREQB Programming of the 2nd carrier frequency, switch to this carrier frequency by setting bit
FREQSEL = 1.
PLLRANGING Initiate VCO autoranging and check results
RF Output Stage (ANTP/ANTN)
The AX5031 uses fully differential antenna pins.
The PA drives the signal generated by the frequency
generation subsystem out to the differential antenna
terminals. The output power of the PA is programmed via
bits TXRNG[3:0] in the register TXPWR. Output power as
well as harmonic content will depend on the external
impedance seen by the PA, recommendations are given in
the section Application Information.
Encoder
The encoder is located between the Framing Unit and the
Modulator. It can optionally transform the bitstream in the
following ways:
It can invert the bit stream.
It can perform differential encoding. This means that a
zero is transmitted as no change in the level, and a one
is transmitted as a change in the level. Differential
encoding is useful for PSK, because PSK transmissions
can be received either as transmitted or inverted, due to
the uncertainty of the initial phase. Differential
encoding / decoding removes this uncertainty.
It can perform Manchester encoding. Manchester
encoding ensures that the modulation has no DC
content and enough transitions (changes from 0 to 1 and
from 1 to 0) for the demodulator bit timing recovery to
function correctly, but does so at a doubling of the data
rate.
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It can perform Spectral Shaping. Spectral Shaping
removes DC content of the bit stream, ensures
transitions for the demodulator bit timing recovery, and
makes sure that the transmitted spectrum does not have
discrete lines even if the transmitted data is cyclic. It
does so without adding additional bits, i.e. without
changing the data rate. Spectral Shaping uses a self
synchronizing feedback shift register.
The encoder is programmed using the register
ENCODING, details and recommendations on usage are
given in the AX5031 Programming Manual.
Framing and FIFO
Most radio systems today group data into packets. The
framing unit is responsible for converting these packets into
a bitstream suitable for the modulator.
The Framing unit supports three different modes:
HDLC
Raw
802.15.4 compliant
The microcontroller communicates with the framing
unit through a 32 level y 10 bit FIFO. The FIFO decouples
microcontroller timing from the radio (modulator) timing.
The bottom 8 bits of the FIFO contain transmit data. The top
2 bit are used to convey meta information in HDLC and
802.15.4 modes. They are unused in Raw mode. The meta
information consists of packet begin / end information and
the result of CRC checks. The FIFO can be written in
powerdown mode.
The FIFO can be operated in polled or interrupt driven
modes. In polled mode, the microcontroller must
periodically read the FIFO status register or the FIFO count
register to determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT
FULL and programmable level interrupts are provided. The
AX5031 signals interrupts by asserting (driving high) its
IRQ line. The interrupt line is level triggered, active high.
Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun,
and the top two bits of the top FIFO word) are also provided
during each SPI access on MISO while the microcontroller
shifts out the register address on MOSI. See the SPI interface
section for details. This feature significantly reduces the
number of SPI accesses necessary.
HDLC Mode
NOTE: HDLC mode follows HighLevel Data Link
Control (HDLC, ISO 13239) protocol.
HDLC Mode is the main framing mode of the AX5031. In
this mode, the AX5031 performs automatic packet
delimiting, and optional packet correctness check by
inserting and checking a cyclic redundancy check (CRC)
field.
The packet structure is given in the following table.
Table 11.
Flag Address Control Information FCS (Optional Flag)
8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit
HDLC packets are delimited with flag sequences of
content 0x7E.
In AX5031 the meaning of address and control is user
defined. The Frame Check Sequence (FCS) can be
programmed to be CRCCCITT, CRC16 or CRC32.
For details on implementing a HDLC communication see
the AX5031 Programming Manual.
Raw Mode
In Raw mode, the AX5031 does not perform any packet
delimiting or byte synchronization. It simply serialises
transmit bytes.
This mode is ideal for implementing legacy protocols in
software.
802.15.4 (ZigBee)
802.15.4 uses binary phase shift keying (PSK) with 300
kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on the
radio. The usable bit rate is only a 15th of the radio bit rate,
however. A spreading function in the transmitter expands
the user bit rate by a factor of 15, to make the transmission
more robust.
In 802.15.4 mode, the AX5031 framing unit performs the
spreading according to the 802.15.4 specification.
The 802.15.4 is a universal DSSS mode, which can be
used with any modulation or data rate as long as it does not
violate the maximum data rate of the modulation being used.
Therefore the maximum DSSS data rate is 16 kbps for FSK
and 40 kbps for ASK and PSK.
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Modulator
Depending on the transmitter settings the modulator
generates various inputs for the PA:
Table 12.
Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate
ASK PA off PA on BW = BITRATE 2000 kBit/s
FSK/MSK/GFSK Df = fdeviation Df = +fdeviation BW = (1 + h) BITRATE 350 kBit/s
PSK DF = 0°DF = 180°BW = BITRATE 2000 kBit/s
h = modulation index. It is the ratio of the
deviation compared to the bitrate;
fdeviation = 0.5hBITRATE
ASK = amplitude shift keying
FSK = frequency shift keying
MSK = minimum shift keying; MSK is a special case
of FSK, where h = 0.5, and therefore
fdeviation = 0.25BITRATE; the advantage of
MSK over FSK is that it can be demodulated
more robustly.
PSK = phase shift keying
OQPSK = offset quadrature shift keying. The AX5031
supports OQPSK. However, unless
compatibility to an existing system is required,
MSK should be preferred.
4FSK = four frequencies are used to transmit two bits
simultaneously during each symbol
Table 13.
Modulation Symbol = 00 Symbol = 01 Symbol = 10 Symbol = 11 Max. Bitrate
4FSK Df = 3fdeviation Df = fdeviation Df = +fdeviation Df = +3fdeviation 400 kBit/s
All modulation schemes are binary.
PWRMODE Register
The PWRMODE register controls, which parts of the chip are operating.
Table 14. PWRMODE REGISTER
PWRMODE Register Name Description Typical Idd
0000 POWERDOWN All digital and analog functions, except the register file, are disabled. The
core supply voltage is reduced to conserve leakage power. SPI registers
are still accessible, but at a slower speed. FIFO access is possible.
0.25 mA
0100 VREGON All digital and analog functions, except the register file, are disabled. The
core voltage, however is at its nominal value for operation, and all SPI
registers are accessible at the maximum speed.
140 mA
0101 STANDBY The crystal oscillator is powered on; the transmitter is off. 500 mA
1100 SYNTHTX The synthesizer is running on the transmit frequency. The transmitter is still
off. This mode is used to let the synthesizer settle on the correct frequency
for transmit.
10 mA
1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode
before the synthesizer has completely settled on the transmit frequency (in
SYNTHTX mode), otherwise spurious spectral transmissions will occur.
11 45 mA
Table 15. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION
Step PWRMODE Remarks
1 POWERDOWN
2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.
4 SYNTHTX The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics
3 FULLTX Data transmission
4 POWERDOWN
AX5031
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Serial Peripheral Interface
The AX5031 can be programmed via a four wire serial
interface according SPI using the pins CLK, MOSI, MISO
and SEL. Registers for setting up the AX5031 are
programmed via the serial peripheral interface in all device
modes.
When the interface signal SEL is pulled low, a 16 bit
configuration data stream is expected on the input signal pin
MOSI, which is interpreted as D0...D7, A0...A6, R_N/W.
Data read from the interface appears on MISO.
Figure 6 shows a write/read access to the interface. The
data stream is built of an address byte including read/write
information and a data byte. Depending on the R_N/W bit
and address bits A[6..0], data D[7..0] can be written via
MOSI or read at the pin MISO.
R_N/W = 0 means read mode, R_N/W = 1 means write
mode.
The read sequence starts with 7 bits of status information
S[6..0] followed by 8 data bits.
The status bits contain the following information:
Table 16.
S6 S5 S4 S3 S2 S1 S0
PLL LOCK FIFO OVER FIFO UNDER FIFO FULL FIFO EMPTY FIFOSTAT(1) FIFOSTAT(0)
SPI Timing
Figure 3. Serial Peripheral Interface Timing
Tsh
R/ W
SS
SCK
MOSI
MISO
A6 A5 A4 A3 A2 A1 D7
A0 D6 D5 D4 D0D1D2D3
D7 D6 D5 D4 D3 D2 D1 D0S6 S5 S4 S3 S2 S1 S0
Tssd Tco
Tss Tck TchTcl ThTs
Tssz
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REGISTER BANK DESCRIPTION
This section describes the bits of the register bank in
detail. The registers are grouped by functional block to
facilitate programming.
No checks are made whether the programmed
combination of bits makes sense! Bit 0 is always the LSB.
NOTES: Whole registers or register bits marked as
reserved should be kept at their default values.
All addresses not documented here must not be
accessed, neither in reading nor in writing.
Table 17. CONTROL REGISTER MAP
Addr Name Dir Reset
Bit
Description
7 6 5 4 3 2 1 0
Revision & Interface Probing
0REVISION R 00100001 SILICONREV(7:0) Silicon Revision
1 SCRATCH RW 11000101 SCRATCH(7:0) Scratch Register
Operating Mode
2PWRMODE RW 0110000 RST REFEN XOEN PWRMODE(3:0) Power Mode
Crystal Oscillator, Part 1
3XTALOSC RW −−−−0010 − − XTALOSCGM(3:0) GM of Crystal Oscillator
FIFO, Part 1
4FIFOCTRL RW −−−−−−11 FIFOSTAT(1:0) FIFO
OVER
FIFO
UNDER
FIFO
FULL
FIFO
EMPTY
FIFOCMD(1:0) FIFO Control
5 FIFODATA RW −−−−−−−− FIFODATA(7:0) FIFO Data
Interrupt Control
6IRQMASK RW 0000000 IRQMASK(6:0) IRQ Mask
7 IRQREQUEST R −−−−−−−− IRQREQUEST(6:0) IRQ Request
Interface & Pin Control
0C PINCFG1 RW 00101000 IRQZ SYSCLK(3:0) Pin Configuration 1
0D PINCFG2 RW 00000000 IRQE − − IRQI Pin Configuration 2
0E PINCFG3 RW 0−−−−−−− reserved SYSCLKR IRQR Pin Configuration 3
0F IRQINVERSION RW 0000000 IRQINVERSION(6:0) IRQ Inversion
Modulation & Framing
10 MODULATION RW 0000010 MODULATION(6:0) Modulation
11 ENCODING RW −−−00010 − − ENC
NOSYNC
ENC
MANCH
ENC
SCRAM
ENC
DIFF
ENC
INV
Encoder/Decoder
Settings
12 FRAMING RW 0000000 HSUPP CRCMODE(1:0) FRMMODE(2:0) Framing settings
14 CRCINIT3 RW 11111111 CRCINIT(31:24) CRC Initialization Data or
Preamble
15 CRCINIT2 RW 11111111 CRCINIT(23:16) CRC Initialization Data or
Preamble
16 CRCINIT1 RW 11111111 CRCINIT(15:8) CRC Initialization Data or
Preamble
17 CRCINIT0 RW 11111111 CRCINIT(7:0) CRC Initialization Data or
Preamble
Voltage Regulator
1B VREG R −−−−−−−− − − SSDS SSREG SDS SREG Voltage Regulator Status
Synthesizer
1C FREQB3 RW 00111001 FREQB(31:24) 2nd Synthesizer Frequency
1D FREQB2 RW 00110100 FREQB(23:16) 2nd Synthesizer Frequency
1E FREQB1 RW 11001100 FREQB(15:8) 2nd Synthesizer Frequency
1F FREQB0 RW 11001101 FREQB(7:0) 2nd Synthesizer Frequency
20 FREQ3 RW 00111001 FREQ(31:24) Synthesizer Frequency
21 FREQ2 RW 00110100 FREQ(23:16) Synthesizer Frequency
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Table 17. CONTROL REGISTER MAP
Addr Description
Bit
ResetDirNameAddr Description
01234567
ResetDirName
22 FREQ1 RW 11001100 FREQ(15:8) Synthesizer Frequency
23 FREQ0 RW 11001101 FREQ(7:0) Synthesizer Frequency
25 FSKDEV2 RW 00000010 FSKDEV(23:16) FSK Frequency Deviation
26 FSKDEV1 RW 01100110 FSKDEV(15:8) FSK Frequency Deviation
27 FSKDEV0 RW 01100110 FSKDEV(7:0) FSK Frequency Deviation
2C PLLLOOP RW 00011101 FREQS
EL
reserved BANDSEL PLLCPI(2:0) FLT(1:0) Synthesizer Loop Filter
Settings
2D PLLRANGING RW 00001000 STICKY
LOCK
PLL
LOCK
RNGERR RNG
START
VCOR(3:0) Synthesizer VCO
AutoRanging
Transmitter
30 TXPWR RW −−−−1000 – – TXRNG(3:0) Transmit Power
31 TXRATEHI RW 00001001 TXRATE(23:16) Transmitter Bitrate
32 TXRATEMID RW 10011001 TXRATE(15:8) Transmitter Bitrate
33 TXRATELO RW 10011010 TXRATE(7:0) Transmitter Bitrate
34 MODMISC RW ––––––11 – reserved PTTLCK
GATE
Misc RF Flags
FIFO, Part 2
35 FIFOCOUNT R −−000000 – – FIFOCOUNT(5:0) FIFO Fill state
36 FIFOTHRESH RW −−000000 – – FIFOTHRESH(5:0) FIFO Threshold
37 FIFOCONTROL
2
RW 0−−−−−00 CLEAR – STOPONERR
(1:0)
Additional FIFO control
Crystal Oscillator, Part 2
4F XTALCAP RW −−000000 – – XTALCAP(5:0) Crystal oscillator tuning
capacitance
4FSK Control
50 FOURFSK RW −−−−−−−0 – FOURFSKENA 4FSK Control
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APPLICATION INFORMATION
Typical Application Diagram
Figure 4. Typical Application Diagram
VDD
ANTP
ANTN
VDD
VREG
CLK16N
MOSI
IRQ
VDD_IO
AX5031
VREG
GND
ANTENNA
TO/FROM MICROCONTROLLER From Power Supply
MISO
CLK16P
1 mF
CLK
SEL
SYSCLK
The GND connection to AX5031 is made via the exposed
center pad of the QFN package. It is mandatory to connect
this pad to GND.
It is mandatory to add 1 mF (low ESR) between VREG and
GND. Decoupling capacitors are not all drawn. It is
recommended to add 100 nF decoupling capacitor for every
VDD and VDD_IO pin. In order to reduce noise on the
antenna inputs it is recommended to add 27 pF on the VDD
pins close to the antenna interface.
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Antenna Interface Circuitry
A small antenna can be directly connected to the AX5031
ANTP and ANTN pins with an optional translation network.
The network must provide DC power to the PA. A biasing
to VREG is necessary.
Beside biasing and impedance matching, the proposed
network also provides low pass filtering to limit spurious
emission.
Singleended Antenna Interface
Figure 5. Structure of the Antenna Interface to 50 W Singleended Equipment or Antenna
CC1 CB1
LT2
IC Antenna
Pins
VRE
G
VREG
LT1
LC2
LC1
CM1
LB1
CB2
LB2
CF1 CF2
LF1
CT1
CT2
CC2
CM2
50 W singleended
equipment or
antenna
Optional filter stage
to suppress TX
harmonics
Table 18.
Frequency Band
LC1,2
[nH]
CC1,2
[pF]
LT1,2
[nH]
CT1,2
[pF]
CM1,2
[pF]
LB1,2
[nH]
CB1,2
[pF]
LF1
[nH]
CF1,2
[pF]
868 / 915 MHz 68 1.2 12 18 2.4 12 2.7 0 WNC
433 MHz 120 2.7 39 7.5 6.0 27 5.2 0 WNC
Voltage Regulator
The AX5031 has an integrated voltage regulator which
generates a stable supply voltage VREG from the voltage
applied at VDD_IO. Use VREG to supply all the VDD
supply pins.
e s n a w w w
AX5031
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19
QFN Soldering Profile
Figure 6. QFN Soldering Profile
Preheat Reflow Cooling
TP
TL
TsMAX
TsMIN
ts
tL
tP
T25°C to Peak
Temperature
Time
25°C
Table 19.
Profile Feature PbFree Process
Average RampUp Rate 3°C/s max.
Preheat Preheat
Temperature Min TsMIN 150°C
Temperature Max TsMAX 200°C
Time (TsMIN to TsMAX) ts60 – 180 sec
Time 25°C to Peak Temperature T25°C to Peak 8 min max.
Reflow Phase
Liquidus Temperature TL217°C
Time over Liquidus Temperature tL60 – 150 s
Peak Temperature tp260°C
Time within 5°C of actual Peak Temperature Tp20 – 40 s
Cooling Phase
Rampdown rate 6°C/s max.
1. All temperatures refer to the top side of the package, measured on the the package body surface.
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QFN Recommended Pad Layout
1. PCB land and solder masking recommendations
are shown in Figure 7.
Figure 7. PCB Land and Solder Mask Recommendations
A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum
B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum
C = Clearance from PCB land edge to solder mask opening to be as tight as possible
to ensure that some solder mask remains between PCB pads.
D = PCB land length = QFN solder pad length + 0.1 mm
E = PCB land width = QFN solder pad width + 0.1 mm
2. Thermal vias should be used on the PCB thermal
pad (middle ground pad) to improve thermal
conductivity from the device to a copper ground
plane area on the reverse side of the printed circuit
board. The number of vias depends on the package
thermal requirements, as determined by thermal
simulation or actual testing.
3. Increasing the number of vias through the printed
circuit board will improve the thermal
conductivity to the reverse side ground plane and
external heat sink. In general, adding more metal
through the PC board under the IC will improve
operational heat transfer, but will require careful
attention to uniform heating of the board during
assembly.
Assembly Process
Stencil Design & Solder Paste Application
1. Stainless steel stencils are recommended for solder
paste application.
2. A stencil thickness of 0.125 – 0.150 mm
(5 – 6 mils) is recommended for screening.
3. For the PCB thermal pad, solder paste should be
printed on the PCB by designing a stencil with an
array of smaller openings that sum to 50% of the
QFN exposed pad area. Solder paste should be
applied through an array of squares (or circles) as
shown in Figure 8.
4. The aperture opening for the signal pads should be
between 5080% of the QFN pad area as shown in
Figure 9.
5. Optionally, for better solder paste release, the
aperture walls should be trapezoidal and the
corners rounded.
6. The fine pitch of the IC leads requires accurate
alignment of the stencil and the printed circuit
board. The stencil and printed circuit assembly
should be aligned to within + 1 mil prior to
application of the solder paste.
7. Noclean flux is recommended since flux from
underneath the thermal pad will be difficult to
clean if watersoluble flux is used.
Figure 8. Solder Paste Application on Exposed Pad
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Figure 9. Solder Paste Application on Pins
Minimum 50% coverage 62% coverage Maximum 80% coverage
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21
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QFN20 4x4, 0.5P
CASE 485EE
ISSUE A
DATE 20 NOV 2015
2.95
20X
0.35
20X
0.50
4.30
0.50
DIMENSIONS: MILLIMETERS
1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
PITCH
PKG
OUTLINE
XXXXXX= Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
XXXXXX
XXXXXX
ALYWG
G
DIM MIN MAX
MILLIMETERS
D4.00 BSC
E4.00 BSC
A0.80 1.00
b0.25 0.35
e0.50 BSC
L1 0.00 0.15
A3 0.20 REF
A1 0.00 0.05
L0.25 0.35
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
D2
E2
1
6
11
20
D2 2.75 2.85
E2 2.75 2.85
e
L1
DETAIL A
L
ALTERNATE
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
A
B
E
D
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X
0.10 C
A
A1
A3
0.08 C
0.10 C
CSEATING
PLANE
SIDE VIEW
DETAIL B
BOTTOM VIEW
b
20X
0.10 B
0.05
AC
CNOTE 3
DETAIL A
(Note: Microdot may be in either location)
L20X
4.30
2.95
GENERIC
MARKING DIAGRAM*
SCALE 2:1
NOTE 4
CONSTRUCTIONS
TERMINAL CONSTRUCTIONS
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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