MAX3232 Datasheet by Texas Instruments

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MAX3232 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver
With ±15-kV ESD Protection
1 Features
• RS-232 Bus-terminal esd protection exceeds
±15 kV using human-body model (HBM)
• Meets or exceeds the requirements of TIA/
EIA-232-F and ITU V.28 standards
• Operates with 3-V to 5.5-V VCC supply
• Operates up to 250 kbit/s
• Two drivers and two receivers
• Low supply current: 300 μA Typical
• External capacitors: 4 × 0.1 μF
• Accepts 5-V logic input with 3.3-V supply
• Alternative high-speed terminal-compatible
devices (1 Mbit/s)
– SN65C3232 (–40°C to 85°C)
– SN75C3232 (0°C to 70°C)
2 Applications
•Industrial PCs
•Wired networking
•Data center and enterprise networking
•Battery-powered systems
•PDAs
•Notebooks
•Laptops
•Palmtop PCs
•Hand-held equipment
3 Description
The MAX3232 device consists of two line drivers,
two line receivers, and a dual charge-pump circuit
with ±15-kV ESD protection terminal to terminal
(serial-port connection terminals, including GND).
The device meets the requirements of TIA/EIA-232-
F and provides the electrical interface between
an asynchronous communication controller and the
serial-port connector. The charge pump and four small
external capacitors allow operation from a single 3-V
to 5.5-V supply. The devices operate at data signaling
rates up to 250 kbit/s and a maximum of 30-V/μs
driver output slew rate.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE
MAX3232
SOIC (D) (16) 9.90 mm × 3.91 mm
SSOP (DB) (16) 6.20 mm × 5.30 mm
SOIC (DW) (16) 10.30 mm × 7.50
mm
TSSOP (PW) (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
spacer
spacer
RX
TX
POWER
3.3 V, 5 V
DIN
ROUT
DOUT
RS232
RIN
RS232
2
2
2
2
Simplified Schematic
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics — Device............................ 5
6.6 Electrical Characteristics — Driver............................. 5
6.7 Electrical Characteristics — Receiver.........................6
6.8 Switching Characteristics............................................6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Standard Application................................................. 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Receiving Notification of Documentation Updates..14
12.2 Support Resources................................................. 14
12.3 Trademarks............................................................. 14
12.4 Electrostatic Discharge Caution..............................14
12.5 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2017) to Revision O (June 2021) Page
• Added Applications: Industrial PCs, Wired networking, and Data center and enterprise computing..................1
• Changed the thermal parameter values for D, DB and PW packages in the Thermal Information table............5
Changes from Revision M (April 2017) to Revision N (June 2017) Page
• Changed the Thermal Information table ............................................................................................................ 5
Changes from Revision L (March 2017) to Revision M (April 2017) Page
• Changed From: "±" To: "to" in the VCC column of Table 9-1 ............................................................................ 12
Changes from Revision K (January 2015) to Revision L (March 2017) Page
• Changed pin 16 (VCC) in Typical Operating Circuit and Capacitor Values .......................................................11
Changes from Revision J (January 2014) to Revision K (January 2015) Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
Changes from Revision I (January 2004) to Revision J (January 2014) Page
• Updated document to new TI data sheet format - no specification changes...................................................... 1
• Deleted Ordering Information table.....................................................................................................................1
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5 Pin Configuration and Functions
1
C1+ 16 VCC
2
V+ 15 GND
3
C1±14 DOUT1
4
C2+ 13 RIN1
5
C2±12 ROUT1
6
V±11 DIN1
7
DOUT2 10 DIN2
8
RIN2 9 ROUT2
Not to scale
Figure 5-1. D, DB, DW, or PW Package, 16-Pin SOIC, SSOP, or TSSOP, Top View
Table 5-1. Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
C1+ 1 — Positive lead of C1 capacitor
V+ 2 O Positive charge pump output for storage capacitor only
C1– 3 — Negative lead of C1 capacitor
C2+ 4 — Positive lead of C2 capacitor
C2– 5 — Negative lead of C2 capacitor
V– 6 O Negative charge pump output for storage capacitor only
DOUT2 7 O RS232 line data output (to remote RS232 system)
DOUT1 14 O RS232 line data output (to remote RS232 system)
RIN2 8 I RS232 line data input (from remote RS232 system)
RIN1 13 I RS232 line data input (from remote RS232 system)
ROUT2 9 O Logic data output (to UART)
ROUT1 12 O Logic data output (to UART)
DIN2 10 I Logic data input (from UART)
DIN1 11 I Logic data input (from UART)
GND 15 — Ground
VCC 16 — Supply Voltage, Connect to external 3 V to 5.5 V power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range(2) –0.3 6 V
V+ Positive output supply voltage range(2) –0.3 7 V
V– Negative output supply voltage range(2) –7 0.3 V
V+ – V– Supply voltage difference(2) 13 V
VIInput voltage range Drivers –0.3 6 V
Receivers –25 25
VOOutput voltage range Drivers –13.2 13.2 V
Receivers –0.3 VCC + 0.3
TJOperating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to network GND.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
RIN , DOUT, and GND pins (1)
15000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
All other pins(1)
3000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(see Typical Operating Circuit and Capacitor Values)(1)
MIN NOM MAX UNIT
VCC Supply voltage VCC = 3.3 V 3 3.3 3.6 V
VCC = 5 V 4.5 5 5.5
VIH Driver high-level input voltage DIN VCC = 3.3 V 2 V
VCC = 5 V 2.4
VIL Driver low-level input voltage DIN 0.8 V
VI
Driver input voltage DIN 0 5.5 V
Receiver input voltage RIN –25 25
TAOperating free-air temperature MAX3232C 0 70 °C
MAX3232I –40 85
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.4 Thermal Information
THERMAL METRIC(1)
MAX3232
UNITSOIC (D) SSOP (DB) SOIC (DW) TSSOP (PW)
16 PINS
RθJA Junction-to-ambient thermal resistance 85.9 103.1 66.6 108.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43.1 49.2 32.4 39.0 °C/W
RθJB Junction-to-board thermal resistance 44.5 54.8 31.9 54.4 °C/W
ψJT Junction-to-top characterization parameter 10.1 12 8.4 3.3 °C/W
ψJB Junction-to-board characterization parameter 44.1 54.1 31.5 53.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics — Device
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2) (see Typical
Operating Circuit and Capacitor Values)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
ICC Supply current No load, VCC = 3.3 V to 5 V 0.3 1 mA
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
6.6 Electrical Characteristics — Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3) (see Typical
Operating Circuit and Capacitor Values)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 V
VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –5.4 V
IIH High-level input current VI = VCC ±0.01 ±1 μA
IIL Low-level input current VI at GND ±0.01 ±1 μA
IOS (2) Short-circuit output current VCC = 3.6 V VO = 0 V ±35 ±60 mA
VCC = 5.5 V VO = 0 V
rOOutput resistance VCC, V+, and V– = 0 V VO = ±2 V 300 10M Ω
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5
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6.7 Electrical Characteristics — Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2) (see Typical
Operating Circuit and Capacitor Values)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V
VOL Low-level output voltage IOL = 1.6 mA 0.4 V
VIT+ Positive-going input threshold voltage VCC = 3.3 V 1.5 2.4 V
VCC = 5 V 1.8 2.4
VIT– Negative-going input threshold voltage VCC = 3.3 V 0.6 1.2 V
VCC = 5 V 0.8 1.5
Vhys Input hysteresis (VIT+ – VIT–) 0.3 V
rIInput resistance VI = ±3 V to ±25 V 3 5 7 kΩ
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
6.8 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3) (see Typical
Operating Circuit and Capacitor Values)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Maximum data rate RL = 3 kΩ, CL = 1000 pF 150 250 kbit/s
One DOUT switching, See Figure 7-1
tsk(p) Driver Pulse skew(2) RL = 3 kΩ to 7 kΩ, CL = 150 to 2500 pF 300 ns
See Figure 7-2
SR(tr) Slew rate, transition region
(see Figure 7-1)
RL = 3 kΩ to 7 kΩ,
VCC = 5 V
CL = 150 to 1000 pF 6 30 V/μs
CL = 150 to 2500 pF 4 30
tPLH®)
Propagation delay time, low- to high-
level output CL = 150 pF
300
ns
tPHL®)
Propagation delay time, high- to low-
level output 300
tsk(p) Receiver Pulse skew(3) 300
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.9 Typical Characteristics
0
1
2
3
4
5
6
0 5 10 15 20 25
VOH (V)
Output Current (mA)
VOH
C001
VCC = 3.3 V
Figure 6-1. DOUT VOH vs Load Current, Both Drivers Loaded
±6
±5
±4
±3
±2
±1
0
1
0 5 10 15 20 25
VOL (V)
Output Current (mA)
VOL
C001
VCC = 3.3 V
Figure 6-2. DOUT VOL vs Load Current, Both Drivers Loaded
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7 Parameter Measurement Information
50 Ω
TEST CIRCUIT VOLTAGE WAVEFORMS
0 V
3 V
Output
Input
VOL
VOH
tTLH
Generator
(see Note B)
RL
RS-232
Output
tTHL
CL
(see Note A)
SR(tr) = 6 V
tTHL or tTLH
1.5 V 1.5 V
3 V
−3 V
3 V
−3 V
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-1. Driver Slew Rate
TEST CIRCUIT VOLTAGE WAVEFORMS
0 V
3 V
Output
Input
VOL
VOH
tPLH
tPHL
50% 50%
1.5 V 1.5 V
50 Ω
Generator
(see Note B)
RL
RS-232
Output
CL
(see Note A)
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-2. Driver Pulse Skew
TEST CIRCUIT VOLTAGE WAVEFORMS
50 Ω
50%
50%
−3 V
3 V
1.5 V
1.5 V
Output
Input
VOL
VOH
tPHL
Generator
(see Note B) tPLH
Output
CL
(see Note A)
A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-3. Receiver Propagation Delay Times
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8 Detailed Description
8.1 Overview
The MAX3232 device consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV
ESD protection terminal to terminal (serial-port connection terminals, including GND). The device meets the
requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication
controller and the serial-port connector. The charge pump and four small external capacitors allow operation
from a single 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s and a maximum of
30-V/μs driver output slew rate. Outputs are protected against shorts to ground.
8.2 Functional Block Diagram
RX
TX
POWER
3.3 V, 5 V
DIN
ROUT
DOUT
RS232
RIN
RS232
2
2
2
2
8.3 Feature Description
8.3.1 Power
The power block increases, inverts, and regulates voltage at V+ and V- pins using a charge pump that requires
four external capacitors.
8.3.2 RS232 Driver
Two drivers interface standard logic level to RS232 levels. Both DIN inputs must be valid high or low.
8.3.3 RS232 Receiver
Two receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT.
Each RIN input includes an internal standard RS232 load.
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8.4 Device Functional Modes
Table 8-1. Each Driver(1)
INPUT
DIN
OUTPUT
DOUT
L H
H L
(1) H = high level, L = low level
Table 8-2. Each
Receiver(1)
INPUT
RIN
OUTPUT
ROUT
L H
H L
Open H
(1) H = high level, L = low level,
Open = input disconnected
or connected driver off
8.4.1 VCC powered by 3 V to 5.5 V
The device will be in normal operation.
8.4.2 VCC unpowered, VCC = 0 V
When MAX3232 is unpowered, it can be safely connected to an active remote RS232 device.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
For proper operation, add capacitors as shown in Typical Operating Circuit and Capacitor Values.
9.2 Standard Application
ROUT and DIN connect to UART or general purpose logic lines. RIN and DOUT lines connect to a RS232
connector or cable.
† C3 can be connected to VCC or GND.
A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as
shown.
Figure 9-1. Typical Operating Circuit and Capacitor Values
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9.2.1 Design Requirements
• Recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible
• Maximum recommended bit rate is 250 kbit/s.
Table 9-1. VCC vs Capacitor Values
VCC C1 C2, C3, C4
3.3 V ± 0.3 V 0.1 µF 0.1 µF
5 V ± 0.5 V 0.047 µF 0.33 µF
3 V to 5.5 V 0.1 µF 0.47 µF
9.2.2 Detailed Design Procedure
• All DIN, FORCEOFF and FORCEON inputs must be connected to valid low or high logic levels.
• Select capacitor values based on VCC level for best performance.
9.2.3 Application Curves
±9
±8
±7
±6
±5
±4
±3
±2
±1
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7 8 9 10
Voltage (V)
Time (s)
DIN
DOUT to RIN
ROUT
C001
VCC = 3.3 V
Figure 9-2. 250 kbit/s Driver to Receiver Loopback Timing Waveform
10 Power Supply Recommendations
VCC should be between 3 V and 5.5 V. Charge pump capacitors should be chosen using table in Typical
Operating Circuit and Capacitor Values.
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11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise
and fall times.
11.2 Layout Example
VCC
Ground
Ground
14
13
15
12
11
10
9
1
2
3
4
5
6
7
8
16
C2
C1
Ground
C3
C4
0.1µF
C1+
V+
C1–
C2+
C2–
V–
DOUT2
RIN2
VCC
GND
DOUT1
RIN1
ROUT1
DIN1
DIN2
ROUT2
Figure 11-1. Layout Diagram
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
MAX3232CDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MA3232C Samples
MAX3232CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 MAX3232C Samples
MAX3232CDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232C Samples
MAX3232CDWG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232C Samples
MAX3232CDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 MAX3232C Samples
MAX3232CPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 MA3232C Samples
MAX3232CPWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MA3232C Samples
MAX3232CPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MA3232C Samples
MAX3232ID NRND SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB3232I Samples
MAX3232IDBRE4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB3232I Samples
MAX3232IDE4 NRND SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDG4 LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDR LIFEBUY SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDRE4 LIFEBUY SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDRG4 LIFEBUY SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I
MAX3232IDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I Samples
MAX3232IDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 MAX3232I Samples
MAX3232IDWRE4 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I Samples
MAX3232IDWRG4 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232I Samples
MAX3232IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 MB3232I Samples
MAX3232IPWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB3232I Samples
Addendum-Page 1
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jan-2023
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
MAX3232IPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MB3232I Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MAX3232 :
•Enhanced Product : MAX3232-EP
Addendum-Page 2
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jan-2023
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2023
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MAX3232CDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
MAX3232CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MAX3232CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232CPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232IDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
MAX3232IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232IDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232IDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MAX3232IDWRG4 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MAX3232IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2023
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MAX3232IPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232IPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MAX3232CDBR SSOP DB 16 2000 356.0 356.0 35.0
MAX3232CDR SOIC D 16 2500 356.0 356.0 35.0
MAX3232CDR SOIC D 16 2500 340.5 336.1 32.0
MAX3232CDWR SOIC DW 16 2000 350.0 350.0 43.0
MAX3232CPWR TSSOP PW 16 2000 364.0 364.0 27.0
MAX3232CPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232CPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232CPWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232IDBR SSOP DB 16 2000 356.0 356.0 35.0
MAX3232IDR SOIC D 16 2500 340.5 336.1 32.0
MAX3232IDRG4 SOIC D 16 2500 340.5 336.1 32.0
MAX3232IDWR SOIC DW 16 2000 350.0 350.0 43.0
MAX3232IDWRG4 SOIC DW 16 2000 350.0 350.0 43.0
MAX3232IPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232IPWR TSSOP PW 16 2000 364.0 364.0 27.0
MAX3232IPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232IPWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232IPWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
Pack Materials-Page 3
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2023
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
MAX3232CDW DW SOIC 16 40 506.98 12.7 4826 6.6
MAX3232CDWG4 DW SOIC 16 40 506.98 12.7 4826 6.6
MAX3232ID D SOIC 16 40 507 8 3940 4.32
MAX3232IDE4 D SOIC 16 40 507 8 3940 4.32
MAX3232IDG4 D SOIC 16 40 507 8 3940 4.32
MAX3232IDW DW SOIC 16 40 506.98 12.7 4826 6.6
Pack Materials-Page 4
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
0.25
0.09
B5.6
5.0
NOTE 4
A
6.5
5.9
NOTE 3
0.95
0.55
SSOP - 2 mm max heightDB0016A
SMALL OUTLINE PACKAGE
4220763/A 05/2022
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 1.500
HEEE gmfim$ WEE
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.85)
16X (0.45)
14X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0016A
SMALL OUTLINE PACKAGE
4220763/A 05/2022
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.85)
16X (0.45)
14X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0016A
SMALL OUTLINE PACKAGE
4220763/A 05/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
SOIC - 2.65 mm max heightDW 16
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
4224780/A
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£3ng
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Egg e %
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
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