ONET8501V Datasheet by Texas Instruments

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FEATURES
APPLICATIONS
DESCRIPTION
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007www.ti.com
11.3 Gbps Differential VCSEL Driver With Output Waveform Shaping
Output Polarity SelectUp to 11.3 Gbps Operation Single 3.3V Supply2-Wire Digital Interface Operating Temperature – 40 °C to 85 °CDigitally Selectable Modulation Current up to Surface Mount Small Footprint 4mm ×4mm 2024 mApp Differential Pin RoHS compliant QFN PackageDigitally Selectable Bias Current up to 20 mAAutomatic Power Control (APC) Loop
10 Gigabit Ethernet Optical TransmittersSupports Transceiver Management System
8x and 10x Fibre Channel Optical Transmitters(TMS)
SONET OC-192/SDH STM-64 OpticalProgrammable Input Equalizer
TransmittersOutput Waveform Control
SFP+ and XFP Transceiver ModulesIncludes Laser Safety Features
XENPAK, XPAK, X2 and 300-pin MSAAnalog Temperature Sensor Output
Transponder ModulesSelectable Monitor Photodiode Current Range
The ONET8501V is a high-speed, 3.3V laser driver designed to directly modulate VCSELs at data rates from2 Gbps up to 11.3 Gbps.
The device provides a two-wire serial interface which allows digital control of the modulation and bias currents,eliminating the need for external components. Output waveform control, in the form of cross point control andindependent over- and undershoot capability on the rising and falling edges is also available to improve VCSELedge speeds and the optical eye diagram. An optional input equalizer can be used for equalization of up to300mm (12 inch) of microstrip or stripline transmission line on FR4 printed circuit boards.
The ONET8501V includes an integrated automatic power control (APC) loop as well as circuitry to support lasersafety and transceiver management systems. The VCSEL driver is characterized for operation from – 40 °C to85 °C ambient temperatures and is available in a small footprint 4mm ×4mm 20 pin RoHS compliant QFNpackage.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
+
++
+
Limiter
DCOffsetCancellation
Equalizer OutputDriver
Over- / Undershoot
Generation
MainDriver
PeakDriver
Delay
Buffer
ShapeControl
Boost
50 W
VCC
100 W
Equalizer
Adjustable
Boost
OSWidth
USWidth
OSHeight
USHeight
CP Adjust
IMOD
IBIAS
Settings
Cp Adjust
Cp Adjust
Power-On
Reset
Band-Gap &
AnalogReferences
TSShift
TSSlope
Bias
Current
Generator
& APC
2-WireInterface & ControlLogic
SDA
SCK
DIS
Temperature
Sensor
COMP
MONB
MONP
FLT
PD
BIAS
DIN+
DIN-
SDA
SCK
DIS
MOD+
MOD-
BIAS
MONB
MONP
FLT
PD
COMP
RZTC
TS
BGV
RZTC
BGV
TS
50 W
8BitRegister
4Bit
4Bit
4Bit
4Bit
7Bit+Sign
8BitRegister
8BitRegister
8BitRegister
4Bit+Sign
4Bit+Sign
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
A simplified block diagram of the ONET8501V is shown in Figure 1 .
The VCSEL driver consists of an equalizer, a limiter, a waveform shaping block with over- and undershootcontrol, an output driver, power-on reset circuitry, a 2-wire serial interface including a control logic block, amodulation current generator and a bias current generator with automatic power control loop, and an analogreference block.
Figure 1. Simplified Block Diagram of the ONET8501V
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DIS
RZTC
TS
SCK
SDA BGV
PD
COMP
MONP
MONB
2
1
3
4
5
14
15
13
12
11
76 8 9 10
1920 18 17 16
VCC
MOD+
MOD-
VCC
BIAS
GND
DIN+
DIN-
GND
FLT
ONET
8501V
20PinQFN
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
PACKAGE
The ONET8501V is packaged in a small footprint 4mm ×4mm 20 pin RoHS compliant QFN package with a leadpitch of 0,5 mm. The pin out is shown below.
20 PIN QFN PACKAGE4 mm ×4 mm (TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
PIN NAME TYPE DESCRIPTIONNO.
1 DIS Digital-in Disables bias, modulation and peaking currents when set to high state. Toggle to reset a fault condition.Recommend shorting pin to GND if disable feature is not used.
2 RZTC Analog Connect external zero TC 28.7k Ω resistor to ground (GND). Used to generate a defined zero TCreference current for internal DACs.
3 TS Analog-out Temperature sensor output.
4 SCK Digital -in 2-wire interface serial clock. Includes a pull-up resistor to VCC.
5 SDA Digital -in 2-wire interface serial data input. Includes a pull-up resistor to VCC.
6, 9, EP GND Supply Circuit ground. Exposed die pad (EP) must be grounded.
7 DIN+ Analog-in Non-inverted data input. On-chip differentially 100 terminated to DIN . Must be AC coupled.
8 DIN – Analog-in Inverted data input. On-chip differentially 100 terminated to DIN+. Must be AC coupled.
10 FLT Digital-out Fault detection flag. LVCMOS output with source and sink capability.
11 BGV Anolog-out Buffered bandgap voltage with 1.16V output. This is a replica of the bandgap voltage at RZTC. For bestmatching, use the same 28.7k Ωresistor to GND as used at RZTC.
12 MONB Bias current monitor. Sources a 3.5% replica of the bias current. Connect an external resistor to ground(GND). If the voltage at this pin exceeds 1.16V a fault is triggered. Typically choose a resistor to giveMONB voltage of 0.8V at the maximum desired bias current.Analog-out13 MONP Photodiode current monitor. Sources a 27% replica of the photodiode current when PDR = 10, a 54%replica when PDR = 01, and a 270% replica when PDR=00. Connect an external resistor (5k typical) toground (GND).
14 COMP Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01 μF capacitor to ground.
15 PD Photodiode input. Pin can source or sink current dependent on register setting.Analog16 BIAS Sinks average bias current for VCSEL in both APC and open loop modes. Connect to laser cathodethrough an inductor. BLM15HG102SN1D recommended.
17, 20 VCC Supply 3.3V ± 10% supply voltage
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
PIN NAME TYPE DESCRIPTIONNO.
18 MOD Inverted modulation current output. On-chip 50 back-terminated to VCC. I
MOD
flows into this pin wheninput data is low.CML-out
(current)19 MOD+ Non-inverted modulation current output. On-chip 50 back-terminated to VCC. I
MOD
flows into this pinwhen input data is high.
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
CC
Supply voltage
(2)
– 0.3 to 4 V
V
DIS
, V
RZTC
, V
TS
, V
SCK
,V
SDA
, V
FLT
, V
BGV
, V
MONB
, Voltage at DIS, RZTC, TS, SCK, SDA, FLT, BGV, MONB, MONP, CAPC,
– 0.3 to 4 VV
MONP
, V
CAPC
, V
PD
, V
BIAS
PD, BIAS, DIN+, DIN , MOD+, MOD
(2)
V
DIN+
, V
DIN –
, V
MOD+
, V
MOD –
I
DIN –
, I
DIN+
Maximum current at input pins 25 mA
I
MOD+
, I
MOD –
Maximum current at output pins 30 mA
ESD ESD rating at all pins 2 kV (HBM)
T
J,max
Maximum junction temperature 125 °C
T
STG
Storage temperature range – 65 to 150 °C
T
A
Characterized free-air operating temperature range – 40 to 85 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability(2) All voltage values are with respect to network ground terminal
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
V
CC
Supply voltage 2.95 3.3 3.6 V
V
IH
Digital input high voltage DIS, SCK, SDA 2 V
V
IL
Digital input low voltage DIS, SCK, SDA 0.8 V
Bias output headroom voltage V
BIAS
– GND 300 mV
High step size mode, min. step size = 5 μA 25 μA
High step size mode, max. step size = 5 μA 1280
Medium step size mode, min. step size = 2.5 μA 12.5Photodiode current range
Medium step size mode, max. step size = 2.5 μA 640
Low step size mode, min. step size = 0.5 μA 2.5
Low step size mode, max. step size = 0.5 μA 128
R
RZTC
Zero TC resistor value
(1)
1.16 V bandgap bias across resistor, E96, 1% accuracy 28.4 28.7 29 k
v
IN
Differential input voltage swing 100 1200 mV
pp
t
R-IN
Input rise time 20% – 80% 30 55 ps
t
F-IN
Input fall time 20% – 80% 30 55 ps
T
A
Operating free-air temperature – 40 85 °C
(1) Changing the value will alter the DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Over recommended operating conditions, all values are for open-loop operation, I
MODC
= 12 mA, I
BIASC
= 6 mA, andR
RZTC
= 28.7 k , unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.95 3.3 3.6 V
I
MODC
= 12 mA, I
BIASC
= 6 mA, including I
MODC
, No waveform 50 70shaping, EQENA = 0
I
MODC
= 12 mA, I
BIASC
= 6 mA, including I
MODC
, No waveform 55 75shaping, EQENA = 1
I
VCC
Supply current I
MODC
= 12 mA, I
BIASC
= 6 mA, including I
MODC
, Single sided max 75 90 mAoutput waveform shaping at MOD+ or MOD , EQENA = 1
I
MODC
= 12 mA, I
BIASC
= 6 mA, including I
MODC
, Double sided max 82 100output waveform shaping at MOD+ or MOD , EQENA = 1
Disabled (DIS=HIGH) or ENA=LOW, EQENA = 0 24
R
IN
Data input resistance Differential between DIN+ / DIN 80 100 120
R
OUT
Data output resistance Single-ended to VCC 40 50 60
Digital input current SCK, SDA, pull up to VCC
(1)
– 10 10 μA
Digital input current DIS, pull down to GND
(1)
– 10 10 μA
V
OH
Digital output high voltage FLT, pull-up to V
CC
, I
SOURCE
= 1000 μA
(2)
2.4 V
V
OL
Digital output low voltage FLT, pull-up to V
CC
, I
SINK
= 1000 μA
(2)
0.4 V
I
BIAS-DIS
Bias current during disable 100 μA
I
BIAS-MIN
Minimum bias current See
(3)
200 μA
I
BIAS-MAX
Maximum bias current DAC set to maximum, open and closed loop 17 20 mA
V
PD
Photodiode reverse bias voltage APC active, I
PD
= max 1.3 2.3 V
Photodiode fault current level 150%Percent of target I
PD
(1)
V
TS
Temperature sensor voltage range 0.5 2.5 V– 40 °C to 120 °C junction temperature. With Mid scale calibration
(1)
Temperature sensor accuracy ± 4 °CWith mid scale calibration
(1)
I
TS
Temperature sensor drive current 100 μASource or sink
(1)
I
MONP
/ I
PD
with control bit PDR = 10 20% 27% 32%
Photodiode current monitor ratio I
MONP
/ I
PD
with control bit PDR = 01 40% 54% 65%
I
MONP
/ I
PD
with control bit PDR = 00 200% 270% 350%
Bias current monitor ratio I
MONB
/ I
BIAS
(nominal 1/30 = 3.3%) 1.2 k sense resistor. 2.9% 3.5% 4.2%
V
CC-RST
VCC reset threshold voltage V
CC
voltage level which triggers power-on reset 2.4 2.5 2.8 V
V
CC-RSTHYS
VCC reset threshold voltage 100 mVhysteresis
V
MONB-FLT
Fault voltage at MONB Fault occurs if voltage at MONB exceeds value 1.1 1.16 1.2 V
(1) Specified by simulation over process, supply and temperature variation(2) External pull up resistor according to timing requirements(3) The bias current can be set below the specified minimum according to the corresponding register setting, however in closed loopoperation settings below the specified value may trigger a fault.
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AC ELECTRICAL CHARACTERISTICS
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Over recommended operating conditions with 50 output load, open loop operation, I
MODC
= 12 mA, I
BIAS
= 6 mA, andR
RZTC
= 28.7 k , unless otherwise noted. Typical operating condition is at V
CC
= 3.3V and T
A
= 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.01 GHz < f < 3.9 GHz 16
SDD11 Differential input return gain 3.9 GHz < f < 11.1 GHz
(1)
dB
11.1 GHz < f < 20 GHz 3
SCD11 Differential to common mode f < 8.25 GHz 35
dBconversion gain
8.25 GHz < f < 20 GHz 28
20% – 80%, t
R-IN
< 40 ps, 100 differential load, no waveformt
R-OUT
Output rise time 24 30shaping, EQENA = 0, 100 mVpp differential input voltage
psOutput fall time 20% – 80%, t
F-IN
< 40 ps, 100 differential load, no waveform 24 30t
F-OUT
shaping, EQENA = 0, 100 mVpp differential input voltage
I
MOD-MAX
Maximum modulation current Output stage tail current 16 24 mA
I
MOD-STEP
Modulation current step size full 100
μAModulation current step size half Modulation current smaller than 6 mA 50
EQENA = 0, K28.5 pattern at 11.3 Gbps, no waveform shaping, 3.5 9100 mVpp, 600 mVpp, 1200 mVpp differential input voltage
DJ Deterministic output jitter ps
p-pEQENA = 1, K28.5 pattern at 11.3 Gbps, maximum equalizationwith 12 ” transmission line at the input, no waveform shaping, 8.5 15200 mVpp, 600 mVpp, 1200 mVpp differential input voltage
Maximum output peaking width 120Maximum peaking height
(2)
psMinimum output peaking width 30
Referred to output stage tail current, high range 10Maximum output peaking height mAReferred to output stage tail current, low range 5
Referred to output stage tail current, high range 0.66Output peaking height step size mAReferred to output stage tail current, low range 0.33
Cross point range 600 mVpp differential input 30 – 70%
RJ Random output jitter 50 load, EQENA = 0, 100 mVpp differential input voltage 0.4 0.6 ps
RMS
τ
APC
APC time constant C
APC
0.01 μF, I
PD
= 100 μA, PD coupling ratio CR = 40
(2)
200 μs
t
OFF
Transmitter disable time Rising edge of DIS to I
BIAS
0.1 ×I
BIAS-NOMINAL
(2)
1 5 μs
t
ON
Disable negate time Falling edge of DIS to I
BIAS
0.9 ×I
BIAS-NOMINAL
(2)
1 ms
t
INIT1
Power-on to initialize Power-on to registers ready to be loaded 0.2 1 ms
t
INIT2
Initialize to transmit Register load STOP command to part ready to transmit valid data
(2)
2 ms
t
RESET
DIS pulse width Time DIS must held high to reset part
(2)
100 ns
t
FAULT
Fault assert time Time from fault condition to FLT high
(2)
50 μs
(1) Differential Return Gain given by SDD11 = – 14 + 13.33 log
10
(f/5.5), f in GHz(2) Assured by simulation over process, supply and temperature variation
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DETAILED DESCRIPTION
EQUALIZER
LIMITER
OUTPUT SIGNAL WAVEFORM SHAPING
HIGH-SPEED OUTPUT DRIVER
MODULATION CURRENT GENERATOR
DC OFFSET CANCELLATION AND CROSS POINT CONTROL
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
The data signal can be applied to an input equalizer by means of the input signal pins DIN+/DIN , which provideon-chip differential 100 line-termination. The equalizer is enabled by setting the EQENA = 1 (bit 1 of register 0).Equalization of up to 300mm (12 ) of microstrip or stripline transmission line on FR4 printed circuit boards can beachieved. The amount of equalization is digitally controlled by the two-wire interface and control logic block anddepends on the register settings EQADJ[0..7] (register 3). The equalizer can also be turned off and bypassed bysetting EQENA = 0. For details about the equalizer settings, see Table 16 .
By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the inputequalization and provides the input signal for the output signal waveform shaping.
The output signal waveform shaping provides two paths for the data signal. The delay buffer ensures that bothpaths have the same transit time. The over- and undershoot peaking width and height are controlled through thetwo wire interface and the peak driver linearly amplifies the signal. The resultant waveform shaped signal is thenadded to the output of the main driver. The overshoot width is controlled by register 5 settings OSW[0..3] and theovershoot height is controlled by register 6 settings OSH[0..3]. The undershoot width is controlled by register 7settings USW[0..3] and the undershoot height is controlled by register 8 settings OSH[0..3].
The peaking current is disabled by setting both over- and undershoot height registers to zero. The peakingcurrent is also disabled when the DIS pin is set to a high level or during a fault condition if the fault detectionenable register flag FLTEN is set (bit 3 of register 0).
The modulation current is sunk from the common emitter node of the output driver differential pair by means of amodulation current generator, which is digitally controlled by the 2-wire serial interface.
The collector nodes of the output stages are connected to the output pins MOD+/ MOD , which include on-chip 2×50 back-termination to VCC. The 50 back-termination together with an optional off chip series resistor helpsto sufficiently suppress signal distortion caused by double reflections for VCSEL diodes with impedances from50 through 110 . The polarity of the output can be selected with the output polarity switch POL (bit 4 ofregister 9).
The modulation current generator provides the current for the current modulator described above. The circuit isdigitally controlled by the 2-wire interface block.
An 8-bit wide control bus, MODC[0..7] (register 1), is used to set the desired modulation current. Furthermore,four modulation current ranges can be selected by means of MODRNG1 (bit 1 of register 13) and MODRNG0 (bit0 of register 13).
The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current isalso disabled in a fault condition if the fault detection enable register flag FLTEN is set (bit 3 of register 0).
The ONET8501V has DC offset cancellation to compensate for internal offset voltages. The offset cancellationcan be disabled by setting OCDIS = 1 (bit 2 of register 9). Disabling the offset cancellation enables the outputcrossing point to be adjusted from 35% to 65% of the output eye diagram. The crossing point can be movedtoward the one level be setting CPSGN = 1 (bit 7 of register 4) and it can be moved toward the zero level bysetting CPSGN = 0. The percentage of shift depends upon the register settings CPADJ[0..6] (register 4).
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BIAS CURRENT GENERATION AND APC LOOP
ANALOG REFERENCE AND TEMPERATURE SENSOR
POWER-ON RESET
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
The bias current generation and APC loop are controlled by means of the 2-wire interface. In open loopoperation, selected by setting OLENA = 1 (bit 4 of register 0) the bias current is set directly by the 8-bit widecontrol word BIASC[0..7] (register 2). In automatic power control mode, selected by setting OLENA = 0, the biascurrent depends on the register settings BIASC[0..7] and the coupling ratio (CR) between the VCSEL biascurrent and the photodiode current. CR = I
BIAS-VCSEL
/ I
PD
.
Three photodiode current ranges can be selected by means of the PDRNG[1..0] bits (register 0). The photodioderange should be chosen to keep the laser bias control DAC, BIASC[0..7], close to the center of its range. Thiskeeps the laser bias current set point resolution high.
For details regarding the bias current setting in open- as well as in closed-loop mode, see Table 16 .
In closed-loop mode, the photodiode polarity bit, PDPOL (bit 0 of register 0), must be set for common-anode orcommon-cathode configuration to ensure proper operation.
The ONET8501V VCSEL driver is supplied by a single 3.3V10% supply voltage connected to the VCC pins. Thisvoltage is referred to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from whichall other internally required voltages and bias currents are derived.
An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground(GND). This resistor is used to generate a precise, zero-TC current which is required as a reference current forthe on-chip DACs.
In order to minimize the module component count, the ONET8501V provides an on-chip temperature sensor.The output voltage of the temperature sensor is available at the TS pin. Due to the die temperature of the 8501Vand for high accuracy applications, the use of an external temperature sensor may be required. However, inorder to improve the part-to-part accuracy of the sensor, the offset voltage and temperature slope can beadjusted through the 2-wire interface. The offset voltage can be adjusted by means of the TSSH[0..3] bits(register 10) and the direction of the offset can be set by the sign bit TSHSGN (bit 4 of register 10). Thetemperature slope can be adjusted by means of the TSSL[0..3] bits (register 11) and the sign bit TSLSGN (bit 4of register 11).
The temperature sensor can be disabled by setting TSDIS = 1 (bit 1 of register 9).
The ONET8501V has power on reset circuitry which ensures that all registers are reset to zero during startup.After the power-on to initialize time (t
INIT1
), the internal registers are ready to be loaded. The part is ready totransmit data after the initialize to transmit time (t
INIT2
), assuming that the chip enable bit ENA is set to 1 and thedisable pin DIS is low.
The ONET8501V can be disabled using either the ENA control register bit or the disable pin DIS. In both casesthe internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back to 1,the part returns to its prior output settings.
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2-WIRE INTERFACE AND CONTROL LOGIC
P S S P
SDA
SCK
tBUF tLOW tRtHIGH tFtHDSTA
tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
The ONET8501V uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, aredriven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include500k Ωpull-up resistors to VCC. For driving these inputs, an open drain output is recommended.
The 2-wire interface allows write access to the internal memory map to modify control registers and read accessto read out the control signals. The ONET8501V is a slave device only which means that it cannot initiate atransmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. Themaster device provides the clock signal as well as the START and STOP commands. The protocol for a datatransmission is as follows:
1. START command
2. 7 bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero indicatesa WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the ONET8501V is I
2
C compatible. The typical timing is shown in Figure 2 and a completedata transfer is shown in Figure 3 . Parameters for Figure 2 are defined in Table 1 .
Bus Idle: Both SDA and SCK lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH,defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGHdefines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master stillwishes to communicate on the bus, it can generate a repeated START condition and address another slavewithout first generating a STOP condition.
Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiveracknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. Thetransmitter releases the SDA line and a device that acknowledges must pull down the SDA line during theacknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of theacknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn ’ tacknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate aSTOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some timelater in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated bythe slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and themaster generates the STOP condition.
Figure 2. I
2
C Timing Diagram
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S
SDA
SCK
P
SLAVE
ADDRESS
ACK
8 9
REGISTER
ADDRESS
ACK ACK
REGISTER
FUNCTION
1-7 1-7 8 9 1-7 8 9
R/W
REGISTER MAPPING
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Table 1. Timing Diagram Definitions
PARAMETER SYMBOL MIN MAX UNIT
SCK clock frequency f
SCK
400 kHz
Bus free time between START and STOP conditions t
BUF
1.3 μs
Hold time after repeated START condition. After this t
HDSTA
0.6 μsperiod, the first clock pulse is generated
Low period of the SCK clock t
LOW
1.3 μs
High period of the SCK clock t
HIGH
0.6 μs
Setup time for a repeated START condition t
SUSTA
0.6 μs
Data HOLD time t
HDDAT
0μs
Data setup time t
SUDAT
100 ns
Rise time of both SDA and SCK signals t
R
300 ns
Fall time of both SDA and SCK signals t
F
300 ns
Setup time for STOP condition t
SUSTO
0.6 μs
Figure 3. Data Transfer
The register mapping for register addresses 0 (0x00) through 13 (0x0D) are shown in Table 2 through Table 15 .Table 16 describes the circuit functionality based on the register settings.
Table 2. Register 0 (0x00) Mapping – Control Settings
Register Address 0 (0x00)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ENA PDRNG1 PDRNG0 OLENA FLTEN PKRNG EQENA PDPOL
Table 3. Register 1 (0x01) Mapping – Modulation Current
Register Address 1 (0x01)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MODC7 MODC6 MODC5 MODC4 MODC3 MODC2 MODC1 MODC0
Table 4. Register 2 (0x02) Mapping – Bias Current
Register Address 2 (0x02)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2 BIASC1 BIASC0
Table 5. Register 3 (0x03) Mapping – Equalizer Adjust
Register Address 3 (0x03)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EQADJ7 EQADJ6 EQADJ5 EQADJ4 EQADJ3 EQADJ2 EQADJ1 EQADJ0
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SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Table 6. Register 4 (0x04) Mapping – Cross Point Adjust
Register Address 4 (0x04)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CPSGN CPADJ6 CPADJ5 CPADJ4 CPADJ3 CPADJ2 CPADJ1 CPADJ0
Table 7. Register 5 (0x05) Mapping – Overshoot Width
Register Address 5 (0x05)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — OSW3 OSW2 OSW1 OSW0
Table 8. Register 6 (0x06) Mapping – Overshoot Height
Register Address 6 (0x06)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — OSH3 OSH2 OSH1 OSH0
Table 9. Register 7 (0x07) Mapping – Undershoot Width
Register Address 7 (0x07)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — USW3 USW2 USW1 USW0
Table 10. Register 8 (0x08) Mapping – Undershoot Height
Register Address 8 (0x08)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — USH3 USH2 USH1 USH0
Table 11. Register 9 (0x09) Mapping – Control Settings
Register Address 9 (0x09)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — POL OCSRC OCDIS TSDIS SPDIS
Table 12. Register 10 (0x0A) Mapping – Temperature Sensor Shift
Register Address 10 (0x0A)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
TSHSGN TSSH3 TSSH2 TSSH1 TSSH0
Table 13. Register 11 (0x0B) Mapping – Temperature Sensor Slope
Register Address 11 (0x0B)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
TSLSGN TSSL3 TSSL2 TSSL1 TSSL0
Table 14. Register 12 (0x0C) Mapping – Cross Point Range
Register Address 12 (0x0C)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — — — CPRNG1 CPRNG0
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SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Table 15. Register 13 (0x0D) Mapping – Modulation Range
Register Address 13 (0x0D)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — — — — MODRNG1 MODRNG0
Table 16. Register Functionality
SYMBOL REGISTER FUNCTION
Enable chip bit:ENA Enable bit 7 1 = chip enabled. Can be toggled low to reset a fault condition0 = chip disabled
Photodiode current range bits:With Coupling Ratio CR between VCSEL bias current and photodiode current= 30PDRNG1 Photodiode current range bit 6
1X = 25 μA – 1280 μA / 5 μA resolutionPDRNG0 Photodiode current range bit 5
01 = 12.5 μA – 640 μA / 2.5 μA resolution00 = 2.5 μA – 128 μA / 0.5 μA resolution
Open loop enable bit:OLENA Open loop enable bit 4 1 = open loop bias current control,0 = closed loop bias current control
Fault detection enable bit:FLTEN Fault detection enable bit 3 1 = fault detection on0 = fault detection off
Laser peaking tail current range (over- and undershoot):PKRNG Peaking tail current range bit 2 1 = 0mA – 12mA0 = 0mA – 6mA
Equalizer enable bitEQENA Equalizer Enable bit 1 1 = equalizer enabled0 = equalizer disabled
Photodiode polarity bit:PDPOL Photodiode polarity bit 0 1 = photodiode cathode connected to V
CC0 = photodiode anode connected to GND
MODC7 Modulation current bit 7 (MSB) Modulation current setting:
MODC6 Modulation current bit 6
MODC5 Modulation current bit 5 MODRNG = 00 (see below); Modulation current: 24 mA / 94 μA steps
MODC4 Modulation current bit 4 MODRNG = 01 (see below): Modulation current: 20 mA / 78 μA steps
MODC3 Modulation current bit 3 MODRNG = 10 (see below); Modulation current: 15.8 mA / 62 μA steps
MODC2 Modulation current bit 2 MODRNG = 11 (see below); Modulation current: 12 mA / 47 μA steps
MODC1 Modulation current bit 1
MODC0 Modulation current bit 0 (LSB)
BIASC7 Bias current bit 7 (MSB) Closed loop (APC):
BIASC6 Bias current bit 6 Coupling ratio CR = I
BIAS-VCSEL
/ I
PD
, BIASC = 0 .. 255, I
BIAS-VCSEL
20mA:
BIASC5 Bias current bit 5
BIASC4 Bias current bit 4 PDRNG = 00 (see above); I
BIAS-VCSEL
= 0.5 μA×CR ×BIASC
BIASC3 Bias current bit 3 PDRNG = 01 (see above); I
BIAS-VCSEL
= 2.5 μA×CR ×BIASC
BIASC2 Bias current bit 2 PDRNG = 1X (see above); I
BIAS-VCSEL
= 5 μA×CR ×BIASC
BIASC1 Bias current bit 1
BIASC0 Bias current bit 0 (LSB) Open loop: I
BIAS-VCSEL
= 86 μA×BIASC
EQADJ7 Equalizer adjustment bit 7 (MSB) Equalizer adjustment setting
EQADJ6 Equalizer adjustment bit 6
EQADJ5 Equalizer adjustment bit 5 EQENA = 0 (see above)
EQADJ4 Equalizer adjustment bit 4 Equalizer is turned off and bypassed
EQADJ3 Equalizer adjustment bit 3
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SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Table 16. Register Functionality (continued)
SYMBOL REGISTER FUNCTION
EQADJ2 Equalizer adjustment bit 2 EQENA = 1 (see above)
EQADJ1 Equalizer adjustment bit 1 Maximum equalization for 00000000
EQADJ0 Equalizer adjustment bit 0 (LSB) Minimum equalization for 11111111
CPSGN Eye crossing sign bit 7 Eye cross-point adjustment setting
CPADJ6 Eye crossing adjustment bit 6 (MSB) CPSGN = 1 (positive shift)
CPADJ5 Eye crossing adjustment bit 5 Maximum shift for 1111111
CPADJ4 Eye crossing adjustment bit 4 Minimum shift for 0000000
CPADJ3 Eye crossing adjustment bit 3 CPSGN = 0 (negative shift)
CPADJ2 Eye crossing adjustment bit 2 Maximum shift for 1111111
CPADJ1 Eye crossing adjustment bit 1 Minimum shift for 0000000
CPADJ0 Eye crossing adjustment bit 0 (LSB)
OSW3 Overshoot width adjustment bit 3 (MSB) Overshoot width adjustment setting
OSW2 Overshoot width adjustment bit 2 Maximum width for 1111
OSW1 Overshoot width adjustment bit 1 Minimum width for 0000
OSW0 Overshoot width adjustment bit 0 (LSB)
OSH3 Overshoot height adjustment bit 3 (MSB) Overshoot height adjustment setting
OSH2 Overshoot height adjustment bit 2 Maximum height for 1111
OSH1 Overshoot height adjustment bit 1 Minimum height for 0000
OSH0 Overshoot height adjustment bit 0 (LSB)
USW3 Undershoot width adjustment bit 3 (MSB) Undershoot width adjustment setting
USW2 Undershoot width adjustment bit 2 Maximum width for 1111
USW1 Undershoot width adjustment bit 1 Minimum width for 0000
USW0 Undershoot width adjustment bit 0 (LSB)
USH3 Undershoot height adjustment bit 3 (MSB) Undershoot height adjustment setting
USH2 Undershoot height adjustment bit 2 Maximum height for 1111
USH1 Undershoot height adjustment bit 1 Minimum height for 0000
USH0 Undershoot height adjustment bit 0 (LSB)
Output polarity switch bitPOL Output polarity switch bit 4 1: pin 18 = MOD+ and pin 19 = MOD-0: pin 18 = MOD- and pin 19 = MOD+
Offset cancellation source bit1: loop connected to the output of the output driver. This requires AC couplingOCSRC Offset cancellation source bit 3
of the output.
0: loop connected to the input of the output driver of the main signal path.
Offset cancellation disable bitOCDIS Offset cancellation disable bit 2 1 = DC offset cancellation is disabled and cross point adjust is enabled0 = DC offset cancellation is enabled and cross point adjust is disabled
TS disable bitTSDIS Temperature sensor disable bit 1 1 = temperature sensor disabled0 = temperature sensor enabled
Signal path disable bitSPDIS Signal path disable bit 0 1 = main signal path is disabled, wave shaping path is enabled0 = main signal path is enabled, wave shaping path is enabled
TSHSGN Temperature sensor shift sign bit 4 Temperature sensor shift adjustment setting
TSSH3 Temperature sensor shift bit 3 TSHSGN = 1 for a positive shift
TSSH2 Temperature sensor shift bit 2 TSHSGN = 0 for a negative shift
TSSH1 Temperature sensor shift bit 1 Maximum shift for 1111
TSSH0 Temperature sensor shift bit 0 Minimum shift for 0000
TSLSGN Temperature sensor slope sign bit 4 Temperature sensor slope adjustment setting
TSSL3 Temperature sensor shift bit 3 TSLSGN = 1 for a positive shift
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LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Table 16. Register Functionality (continued)
SYMBOL REGISTER FUNCTION
TSSL2 Temperature sensor shift bit 2 TSLSGN = 0 for a negative shift
TSSL1 Temperature sensor shift bit 1 Maximum shift for 1111
TSSL0 Temperature sensor shift bit 0 Minimum shift for 0000
Cross point adjustment range bits:CPRNG1 Cross point range bit 1
Minimum adjustment range for 00CPRNG0 Cross point range bit 0
Maximum adjustment range for 11
Modulation current range reduction bits:00 = no reduction in modulation current and step sizeMODRNG1 Modulation current reduction bit 1
01 = current range and step size reduced by a factor of 0.833MODRNG0 Modulation current reduction bit 0
10 = current range and step size reduced by a factor of 0.6611 = current range and step size reduced by a factor of 0.5
The ONET8501V provides built in laser safety features. The following fault conditions are detected:
1. Voltage at MONB exceeds the voltage at RZTC (1.16V),
2. Photodiode current exceeds 150% of its set value,
3. Bias control DAC drops in value by more than 50% in one step
If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET8501V responds by:
1. Setting the VCSEL bias current to zero.
2. Setting the modulation current to zero.
3. Setting the peaking current to zero
4. Asserting and latching the FLT pin.
Fault recovery is performed by the following procedure:
1. The disable pin DIS and/or the internal enable control bit ENA are toggled for at least the fault latch resettime t
RESET
.
2. The FLT pin de-asserts while the disable pin DIS is asserted or the enable bit ENA is de-asserted.
3. If the fault condition is no longer present, the part will return to normal operation with its prior output settingsafter the disable negate time t
ON
.
4. If the fault condition is still present, FLT re-asserts once DIS is set to a low level and the part will not return tonormal operation.
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TYPICAL OPERATION CHARACTERISTICS
0
2
4
6
8
0 5 10 15 20 25
ModulationCurrent-mA
DeterministicJitter-pspp
-40 -20 0 20 40 60 80 100
0
2
4
6
8
DeterministicJitter-pspp
T -Free-AirTemperature-°C
A
0
0.1
0.2
0.3
0.4
0.5
0.6
0 5 10 15 20 25
ModulationCurrent-mA
DeterministicJitter-psrms
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Typical operating condition is at V
CC
= 3.3V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, V
IN
= 600 mVpp and no waveformshaping (unless otherwise noted).
DETERMINISTIC JITTER DETERMINISTIC JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 4. Figure 5.
RANDOM JITTER RANDOM JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 6. Figure 7.
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0
5
10
15
20
25
30
35
0 5 10 15 20 25
ModulationCurrent-mA
FallTime
RiseTime
TransitionTime-ps
0
5
10
15
20
25
30
35
-40 -20 0 20 40 60 80 100
FallTime
T -Free-AirTemperature-°C
A
TransitionTime-ps
RiseTime
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 5 10 15 20 25
BiasCurrent-mA
BiasMonitorCurrent-mA
0
5
10
15
20
25
0 50 100 150 200 250 300
BiasCurrentRegisterSetting(Decimal)
OpenLoopBiasCurrent-mA
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, V
IN
= 600 mVpp and no waveformshaping (unless otherwise noted).
RISE-TIME AND FALL-TIME RISE-TIME AND FALL-TIMEvs vsMODULATION CURRENT TEMPERATURE
Figure 8. Figure 9.
BIAS CURRENT IN OPEN LOOP MODE BIAS-MONITOR CURRENT I
MONBvs vsBIASC REGISTER SETTING BIAS CURRENT
Figure 10. Figure 11.
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0
0.1
0.2
0.3
0.4
0.5
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14
PhotodiodeCurrent-mA
BiasMonitorCurrent-mA
0
5
10
15
20
25
0 50 100 150 200 250 300
ModulationCurrentRegisterSetting(Decimal)
ModulationCurrent-mA
25
30
35
40
45
50
55
60
65
70
75
-40 -20 0 20 40 60 80 100
SupplyCurrent-mA
T -Free-AirTemperature-°C
A
0
0.5
1
1.5
2
TempSensorVoltage-mV
-40 -20 0 20 40 60 80 100
T -Free-AirTemperature-°C
A
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, V
IN
= 600 mVpp and no waveformshaping (unless otherwise noted).
PHOTODIODE-MONITOR CURRENT I
MONP
MODULATION CURRENTvs vsPD CURRENT, PDR = 00 MODC REGISTER SETTING
Figure 12. Figure 13.
SUPPLY CURRENT TEMPERATURE SENSOR VOLTAGE V
TSvs vsTEMPERATURE TEMPERATURE
Figure 14. Figure 15.
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14.8ps/Div
400mv/Div
14.8ps/Div
190mv/Div
14.8ps/Div
190mv/Div
20ps/Div
190mv/Div
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, V
IN
= 600 mVpp and no waveformshaping (unless otherwise noted).
EYE-DIAGRAM AT 11.3GBPS EYE-DIAGRAM AT 11.3GBPSK28.5 PATTERN, I
MOD
=6mA, EQENA = 0 K28.5 PATTERN, I
MOD
=10mA, EQENA = 0
Figure 16. Figure 17.
EYE-DIAGRAM AT 11.3GBPSK28.5 PATTERN, I
MOD
=6mA, EQENA = 0, EYE-DIAGRAM AT 8.5GBPSOSH = USH = 8, OSW = USW = 2, PKRNG = 0 K28.5 PATTERN, I
MOD
=6mA, EQENA = 0
Figure 18. Figure 19.
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14.8ps/Div190mv/Div
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3V, T
A
= 25 °C, I
BIASC
= 6 mA, I
MODC
= 12 mA, V
IN
= 600 mVpp and no waveformshaping (unless otherwise noted).
EYE-DIAGRAM AT 11.3GBPSK28.5 PATTERN, I
MOD
=6mA,EQENA = 1, 12" OF FR4 AT INPUTS
Figure 20.
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APPLICATION INFORMATION
DIN+
DIN-
C1
C2
0.1µF
L1
BLM15HD102SN1
BGV
DIS
MONB
SDA
TS
MONP
RMONB
C3
0.01µF
C4
0.01µF
FLT
SDK
5kΩ
1.2kΩ
C7
28.7kΩ
RZTC
MONP
DIN+
DIN-
MONB
MOD-
MOD+
BIAS
DIS
TS
SCK
SDA
GND VCC
VCC
FLT
RZTC
PD
COMP
ONET8501V
GND
0.1µF
BGV
RMONP
100Ω Diff TL
0.1µF
0.1µF
100nH
LQW15ANR10J00
VCSEL
Monitor
Photodiode
L2
L3
L4
BLM15HD102SN1
VCC
0.1µF
C6
C5 L5
BLM15HG102SN1
0.1µF
C8
0.1µF
C9
100nH
LQW15ANR10J00
Optional
RBGV
28.7kΩ
100Ω Diff TL
VCC
Optional
LAYOUT GUIDELINES
ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Figure 21 shows a typical application circuit using the ONET8501V with a VCSEL diode, anode connected toVCC, and driven differentially. The VCSEL driver is controlled via the 2-wire interface SDA/SCK by amicrocontroller. In a typical application, the FLT, MONP, MONP and TS outputs are also connected to themicrocontroller for transceiver management purposes.
The component values in Figure 21 are typical examples and may be varied according to the intendedapplication. Single-ended VCSEL drive can be done by terminating the unused driver output in a resistance thatmatches the VCSEL series resistance, however, the available VCSEL modulation current will be halved.
Figure 21. Typical Application Circuit With a Differential Driven VCSEL
In the recommended application circuit, the purpose of the optional series resistors is to improve the signalintegrity between the VCSEL driver and the VCSEL. Since the VCSEL impedance varies depending on its type,the series resistor may provide better matching impedance for the modulation current outputs.
For optimum performance, use 50 transmission lines (100 differential) for connecting the signal source to theDIN+ and DIN pins and for connecting the modulation current outputs, MOD+ and MOD , to the VCSEL. Thelength of the transmission lines should be kept as short as possible to reduce loss and pattern-dependent jitter. Itis recommended to assemble the series matching resistors as close as possible to the TOSA.
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ONET8501V
SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2007) to Revision A ......................................................................................................... Page
Changed the I
VCC
MAX supply current (first row) from 85 to 70 mA. ................................................................................... 5Changed the I
VCC
MAX supply current (second row) from 70 to 75 mA. ............................................................................... 5Changed first sentence in the Data Transfer section from "The number of data bytes transferred between a STARTand a STOP condition is not limited and is determined by the master device." .................................................................... 9
Changes from Revision A (July 2007) to Revision B ..................................................................................................... Page
Changed T
STG
Max from 85 °C............................................................................................................................................... 4
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ONET8501VRGPR ACTIVE QFN RGP 20 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ONET
8501V Samples
ONET8501VRGPT ACTIVE QFN RGP 20 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ONET
8501V Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE OPTION ADDENDUM
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PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET8501VRGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ONET8501VRGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET8501VRGPR QFN RGP 20 3000 552.0 367.0 36.0
ONET8501VRGPT QFN RGP 20 250 552.0 185.0 36.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ONET8501VRGPR RGP VQFN 20 3000 381 5.79 2286 0
ONET8501VRGPT RGP VQFN 20 250 381 5.79 2286 0
Pack Materials-Page 3
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VQFN - 1 mm max heightRGP 20
VERY THIN QUAD FLATPACK
4 x 4, 0.5 mm pitch
4224735/A
L
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
PACKAGE OUTLINE
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RGP0020D
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
PIN 1 INDEX AREA
4.1
3.9
4.1
3.9
1 MAX
0.05
0.00 2.8
2.6
2
2
16X 0.5
(0.2) TYP
PIN 1 IDENTIFICATION
(OPTIONAL)
LEAD DETAIL "A"
(0.1) TYP
LEAD DETAIL "A"
OPTION
20X 0.5
0.3
1
5
610
11
15
16
20
20X 0.30
0.18
SYMM
SEATING PLANE
C
21
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
RGP0020D
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
( 2.7)
(2)
(3.8)
(2) (3.8)
(1.1)
(1.1)
20X (0.6)
20X (0.24)
16X (0.5)
(R0.05) TYP
(Ø0.2) VIA
TYP
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
5
1
20 16
15
11
10
6
21
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
EXAMPLE STENCIL DESIGN
4219028/A 12/2018
www.ti.com
VQFN - 1 mm max height
RGP0020D
PLASTIC QUAD FLATPACK- NO LEAD
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED COVERAGE BY AREA
SCALE: 20X
SYMM
SYMM
4X ( 1.19)
(2)
(3.8)
(2) (3.8)
(0.695)
(0.695)
20X (0.6)
20X (0.24)
16X (0.5)
(R0.05) TYP
5
1
20 16
15
11
10
6METAL
TYP
21
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