SI1900DL Datasheet by Vishay Siliconix

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— VISHAYN V RoHS cowmm NALDEEN FREE fl
Vishay Siliconix
Si1900DL
Document Number: 71251
S10-1054-Rev. F, 03-May-10
www.vishay.com
1
Dual N-Channel 30 V (D-S) MOSFET
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
TrenchFET® Power MOSFET
Compliant to RoHS Directive 2002/95/EC
#
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A)
30 0.480 at VGS = 10 V 0.63
0.700 at VGS = 4.5 V 0.52
Marking Code
PB XX
Lot Traceability
and Date Code
Part # Code
YY
Ordering Information: Si1900DL-T1-E3 (Lead (Pb)-free)
Si1900DL-T1-GE3 (Lead (Pb)-free and Halogen-free)
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
S1
G1
D2
D1
G2
S2
Notes:
a. Surface mounted on 1" x 1" FR4 board.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol 5 s Steady State Unit
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)aTA = 25 °C ID
0.63 0.59
A
TA = 85 °C 0.45 0.43
Pulsed Drain Current IDM 1.0
Continuous Source-Current (Diode Conduction)aIS0.25 0.23
Maximum Power DissipationaTA = 25 °C PD
0.30 0.27 W
TA = 85 °C 0.16 0.14
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientat 5 s RthJA
360 415
°C/W
Steady State 400 460
Maximum Junction-to-Foot (Drain) Steady State RthJF 300 350
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Document Number: 71251
S10-1054-Rev. F, 03-May-10
Vishay Siliconix
Si1900DL
Notes
a. Pulse test; pulse width 300 µs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS , ID = 250 µA 1.0 3 V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V 1 µA
VDS = 30 V, VGS = 0 V, TJ = 85 °C 5
On-State Drain CurrentaID(on) V
DS 5 V, VGS = 10 V 1.0 A
Drain-Source On-State ResistanceaRDS(on)
VGS = 10 V, ID = 0.59 A 0.410 0.480 Ω
VGS = 4.5 V, ID = 0.2 A 0.600 0.700
Forward Transconductanceagfs VDS = 10 V, ID = 0.59 A 0.75 S
Diode Forward VoltageaVSD IS = 0.23 A, VGS = 0 V 0.8 1.2 V
Dynamicb
Total Gate Charge Qg
VDS = 15 V, VGS = 10 V, ID = 0.59 A
0.86 1.4
nCGate-Source Charge Qgs 0.24
Gate-Drain Charge Qgd 0.08
Tur n - O n D e lay T i m e td(on)
VDD = 15 V, RL = 30 Ω
ID 0.5 A, VGEN = 10 V, Rg = 6 Ω
510
ns
Rise Time tr 815
Turn-Off Delay Time td(off) 815
Fall Time tf715
Source-Drain Reverse Recovery Time trr IF = 0.23 A, dI/dt = 100 A/µs 15 30
Output Characteristics
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VGS = 10 V thru 4 V
3 V
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)ID
Transfer Characteristics
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
T
C
= 125 °C
- 55 °C
25 °C
V
GS
- Gate-to-Source Voltage (V)
- Drain Current (A)I
D
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Document Number: 71251
S10-1054-Rev. F, 03-May-10
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Vishay Siliconix
Si1900DL
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
On-Resistance vs. Drain Current
Gate Charge
Source-Drain Diode Forward Voltage
0.0
0.4
0.8
1.2
1.6
0.0 0.2 0.4 0.6 0.8 1.0
VGS = 4.5 V
VGS = 10 V
- On-Resistance (Ω)R DS(on)
ID- Drain Current (A)
0
2
4
6
8
10
0.0 0.2 0.4 0.6 0.8 1.0
VDS = 15 V
ID = 0.59 A
- Gate-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
V
GS
0.0 0.2 0.4 0.6 0.81.0 1.2
TJ = 150 °C
TJ = 25 °C
1
0.1
VSD )V( egatloV niarD-ot-ecruoS -
- Source Current (A)IS
Capacitance
On-Resistance vs. Junction Temperature
On-Resistance vs. Gate-to-Source Voltage
0
10
20
30
40
50
60
0 4 8 12 16 20
VDS - Drain-to-Source Voltage (V)
Crss
Coss
Ciss
C - Capacitance (pF)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 0.59 A
TJ- Junction Temperature (°C)
(Normalized)
- On-Resistance
RDS(on)
0.0
0.3
0.6
0.9
1.2
1.5
1.8
0246810
ID = 0.59 A
- On-Resistance (Ω)RDS(on)
VGS - Gate-to-Source Voltage (V)
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Document Number: 71251
S10-1054-Rev. F, 03-May-10
Vishay Siliconix
Si1900DL
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71251.
Threshold Voltage
- 0.6
- 0.4
- 0.2
0
0.2
0.4
- 50 - 25 0 25 50 75 100 125 150
ID = 250 µA
Variance (V)VGS(th)
TJ - Temperature (°C)
Single Pulse Power
0
3
5
1
2
Power (W)
Time (s)
4
1 100 6001010-1
10-2
10-3
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 00601110-1
10-4 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 400 °C/W
3. TJM - T A = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
Normalized Thermal Transient Impedance, Junction-to-Foot
10-3 10-2 01110-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
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c
E
E1
e
D
e1
A2A
A1
1
-A-
b
-B-
23
654
Package Information
Vishay Siliconix
Document Number: 71154
06-Jul-01 www.vishay.com
1
SCĆ70: 6ĆLEADS
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.90 1.10 0.035 0.043
A1 0.10 – 0.004
A20.80 1.00 0.031 0.039
b0.15 0.30 0.006 0.012
c0.10 0.25 0.004 0.010
D1.80 2.00 2.20 0.071 0.079 0.087
E1.80 2.10 2.40 0.071 0.083 0.094
E11.15 1.25 1.35 0.045 0.049 0.053
e0.65BSC 0.026BSC
e11.20 1.30 1.40 0.047 0.051 0.055
L0.10 0.20 0.30 0.004 0.008 0.012
7_Nom 7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
VISHAY
AN814
Vishay Siliconix
Document Number: 71237
12-Dec-03
www.vishay.com
1
Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
This technical note discusses the pin-outs, package outlines,
pad patterns, evaluation board layout, and thermal
performance for dual-channel LITTLE FOOT power
MOSFETs in the SC-70 package. These new Vishay Siliconix
devices are intended for small-signal applications where a
miniaturized package is needed and low levels of current
(around 250 mA) need to be switched, either directly or by
using a level shift configuration. Vishay provides these devices
with a range of on-resistance specifications in 6-pin versions.
The new 6-pin SC-70 package enables improved
on-resistance values and enhanced thermal performance.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
FIGURE 1.
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
S1
G1
D2
D1
G2
S2
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin
SC-70. This basic pad pattern is sufficient for the low-power
applications for which this package is intended. For the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 20% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB).
EVALUATION BOARDS FOR THE DUAL
SC70-6
The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches
by 0.5 inches. The copper pad traces are the same as
described in the previous section, Basic Pad Patterns. The
board allows interrogation from the outer pins to 6-pin DIP
connections permitting test sockets to be used in evaluation
testing.
The thermal performance of the dual SC-70 has been
measured on the EVB with the results shown below. The
minimum recommended footprint on the evaluation board was
compared with the industry standard 1-inch square FR4 PCB
with copper on both sides of the board.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package
measured as junction-to-foot thermal resistance is 300_C/W
typical, 350_C/W maximum. The “foot” is the drain lead of the
device as it connects with the body. Note that these numbers
are somewhat higher than other LITTLE FOOT devices due to
the limited thermal performance of the Alloy 42 lead-frame
compared with a standard copper lead-frame.
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady
state. Maximum ratings are 460_C/W for the dual. All figures
based on the 1-inch square FR4 test board. The following
example shows how the thermal resistance impacts power
dissipation for the dual 6-pin SC-70 package at two different
ambient temperatures.
VISHAY RU 150 C , 25 C AOOVC/W RU 150 C , 60 C 400‘7C/W HHHH HHWH
AN814
Vishay Siliconix
www.vishay.com
2
Document Number: 71237
12-Dec-03
SC-70 (6-PIN)
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
400oCńW
PD+312 mW
PD+TJ(max) *TA
RqJA
PD+150oC*60oC
400oCńW
PD+225 mW
NOTE: Although they are intended for low-power applications,
devices in the 6-pin SC-70 will handle power dissipation in
excess of 0.2 W.
Testing
To aid comparison further, Figure 2 illustrates the dual-channel
SC-70 thermal performance on two different board sizes and
two different pad patterns. The results display the thermal
performance out to steady state. The measured steady state
values of RθJA for the dual 6-pin SC-70 are as follows:
LITTLE FOOT SC-70 (6-PIN)
1) Minimum recommended pad pattern (see
Figure 2) on the EVB of 0.5 inches x
0.6 inches.
518_C/W
2) Industry standard 1” square PCB with
maximum copper both sides. 413_C/W
Time (Secs)
FIGURE 2. Comparison of Dual SC70-6 on EVB and 1”
Square FR4 PCB.
Thermal Resistance (C/W)
0
1
500
100
200
100 1000
300
1010-1
10-2
10-3
10-4
10-5
1” Square FR4 PCB
Dual EVB
400
The results show that if the board area can be increased and
maximum copper traces are added, the thermal resistance
reduction is limited to 20%. This fact confirms that the power
dissipation is restricted with the package size and the Alloy 42
leadframe.
ASSOCIATED DOCUMENT
Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper
Leadframe Version, REcommended Pad Pattern and Thermal
Performance, AN815, (http://www.vishay.com/doc?71334).
Application Note 826 VlSI-MY Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead n 057 (1 702) a use 12 438) Recommended Mwmmum Pads Dwmensmns m Inches/(mm) Documem Number 72502 «may com Rev 5m 2w rJaurOB
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72602
18 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.096
(2.438)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.067
(1.702)
0.026
(0.648)
0.045
(1.143)
0.016
(0.406)
0.026
(0.648)
0.010
(0.241)
Return to Index
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Revision: 08-Feb-17 1Document Number: 91000
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