SI1469DH Datasheet by Vishay Siliconix

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Vishay Siliconix
Si1469DH
Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
www.vishay.com
1
P-Channel 20 V (D-S) MOSFET
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
TrenchFET® Power MOSFET
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
Load Switch for Portable Devices
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)ID (A)cQg (Typ.)
- 20
0.080 at VGS = - 10 V - 2.7
5.5 nC0.100 at VGS = - 4.5 V - 2.7
0.155 at VGS = - 2.5 V - 2.7
Ordering Information: Si1469DH-T1-E3 (Lead (Pb)-free)
Si1469DH-T1-GE3 (Lead (Pb)-free and Halogen-free)
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top V i ew
D
D
G
D
D
S
Marking Code
BL XX
Lot Traceability
and Date Code
Part #
Code
YY
S
G
D
P-Channel MOSFET
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 5 s.
c. Package limited.
d. Maximum under steady state conditions is 125 °C/W.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 20 V
Gate-Source Voltage VGS ± 12
Continuous Drain Current (TJ = 150 °C)a, b
TC = 25 °C
ID
- 2.7c
A
TC = 70 °C - 2.7c
TA = 25 °C - 3.2a, b
TA = 70 °C - 2.6a, b
Pulsed Drain Current (10 µs Pulse Width) IDM - 8
Continuous Source-Drain Diode Currenta, b TC = 25 °C IS
- 2.3
TA = 25 °C - 1.25a, b
Maximum Power Dissipationa, b
TC = 25 °C
PD
2.78
W
TC = 70 °C 1.78
TA = 25 °C 1.5a, b
TA = 70 °C 1a, b
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
Soldering Recommendations (Peak Temperature)c, d 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambienta, d t 5 s RthJA 60 80 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 34 45
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Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
Vishay Siliconix
Si1469DH
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 20 V
VDS Temperature Coefficient ΔVDS/TJ ID = - 250 µA - 21 mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ - 2.4
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.6 - 1.5 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 12 V - 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 20 V, VGS = 0 V - 1 µA
VDS = - 20 V, VGS = 0 V, TJ = 55 °C - 10
On-State Drain CurrentaID(on) V
DS 5 V, VGS = - 4.5 V - 3 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 10 V, ID = - 2.0 A 0.065 0.080
Ω
VGS = - 4.5 V, ID = - 1.8 A 0.081 0.100
VGS = - 2.5 V, ID = - 1.5 A 0.126 0.155
Forward Transconductanceagfs VDS = - 10 V, ID = - 2.0 A 6S
Dynamicb
Input Capacitance Ciss
VDS = - 10 V, VGS = 0 V, f = 1 MHz
470
pFOutput Capacitance Coss 105
Reverse Transfer Capacitance Crss 80
Total Gate Charge Qg
VDS = - 10 V, VGS = - 4.5 V, ID = - 2.5 A
5.5 8.5
nCGate-Source Charge Qgs 0.8
Gate-Drain Charge Qgd 1.7
Gate Resistance Rgf = 1 MHz 10 Ω
Tur n - On D elay T ime td(on)
VDD = - 10 V, RL = 5 Ω
ID - 2 A, VGEN = - 4.5 V, Rg = 1 Ω
27 41
ns
Rise Time tr48 72
Turn-Off Delay Time td(off) 27 41
Fall Time tf15 23
Tur n - On D elay T ime td(on)
VDD = - 10 V, RL = 5 Ω
ID - 2 A, VGEN = - 10 V, Rg = 1 Ω
510
Rise Time tr20 30
Turn-Off Delay Time td(off) 22 33
Fall Time tf918
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C - 1.6 A
Pulse Diode Forward Current ISM - 6.5
Body Diode Voltage VSD IS = - 2 A, VGS = 0 V - 0.83 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 2.0 A, dI/dt = 100 A/µs, TJ = 25 °C
20 30 ns
Body Diode Reverse Recovery Charge Qrr 815nC
Reverse Recovery Fall Time ta7ns
Reverse Recovery Rise Time tb13
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Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
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Vishay Siliconix
Si1469DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
2
4
6
8
10
0.0 0.6 1.2 1.82.4 3.0
VDS - Drain-to-Source Voltage (V)
VGS = 10 V thru 3 V
- Drain Current (A)ID
2 V
0.00
0.04
0.08
0.12
0.16
0.20
0.0 1.4 2.84.2 5.6 7.0
ID - Drain Current (A)
VGS = 4.5 V
- On-Resistance (RDS(on) )
VGS = 2.5 V
VGS = 10 V
0
2
4
6
8
10
0 3 6 9 12 15
Qg - Total Gate Charge (nC)
ID = 2.5 A
- Gate-to-Source Voltage (V)VGS
VDS = 5 V
VDS = 10 V
VDS = 15 V
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
VGS - Gate-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5
= 25 °C
TC
= 125 °C
- Drain Current (A)ID
TC
= - 55 °C
TC
Crss
VDS - Drain-to-Source Voltage (V)
0
160
320
480
640
800
04812 16 20
Coss
Ciss
C - Capacitance (pF)
TJ- Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
ID = 2 A
RDS(on) - On-Resistance
(Normalized)
VGS = 10 V
VGS = 2.5 V
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Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
Vishay Siliconix
Si1469DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
0.0 0.3 0.6 0.9 1.2 1.5
VSD - Source-to-Drain Voltage (V)
- Source Current (A)I
S
0.01
0.1
1
10
TJ = 25 °C
TJ = 150 °C
- 0.2
- 0.1
0.0
0.1
0.2
0.3
0.4
- 50 - 25 0 25 50 75 100 125 150
ID = 250 µA
Variance (V)
VGS(th)
TJ - Temperature (°C)
ID = 5 mA
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
ID = 2 A
VGS - Gate-to-Source Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
0246810
- On-Resistance (RDS(on) )
125 °C
25 °C
0
6
12
18
24
30
011100.0 0.01
Time (s)
Power (W)
0.1
Safe Operating Area, Junction-to-Ambient
VDS
- Drain-to-Source Voltage (V)
* VGS minimum VGS at which RDS(on) is specified
TC = 25 °C
Single Pulse
- Drain Current (A)ID
100 ms
1 s
DC
1 ms
10 ms
Limited by RDS(on)*
0.01
0.1
1
10
0.01 0.1 110 100
10 s
Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
www.vishay.com
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Vishay Siliconix
Si1469DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
ID - Drain Current (A)
TC - Case Temperature (°C)
0
1
2
3
4
5
0 255075100125150
Package Limited
Power Derating, Junction-to-Foot
0.0
0.7
1.4
2.1
2.8
3.5
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Power Dissipation (W)
Power Derating, Junction-to-Ambient
0.00
0.24
0.48
0.72
0.96
1.20
0 25 50 75 100 125 150
TA - Ambient Temperature (°C)
Power Dissipation (W)
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Document Number: 74441
S10-0646-Rev. C, 22-Mar-10
Vishay Siliconix
Si1469DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74441.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 110 100010-1
10-4 100
0.2
0.1
0.05
0.02
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01 Single Pulse
t1
t2
Notes:
PDM
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 125 °C/W
3. TJM - TA = PDMZthJA(t)
t1
t2
4. Surface Mounted
Duty Cycle = 0.5
Normalized Thermal Transient Impedance, Junction-to-Foot
10
-3
10
-2
01110
-1
10
-4
0.2
0.1
0.05
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
0.02
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c
E
E1
e
D
e1
A2A
A1
1
-A-
b
-B-
23
654
Package Information
Vishay Siliconix
Document Number: 71154
06-Jul-01 www.vishay.com
1
SCĆ70: 6ĆLEADS
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.90 1.10 0.035 0.043
A1 0.10 – 0.004
A20.80 1.00 0.031 0.039
b0.15 0.30 0.006 0.012
c0.10 0.25 0.004 0.010
D1.80 2.00 2.20 0.071 0.079 0.087
E1.80 2.10 2.40 0.071 0.083 0.094
E11.15 1.25 1.35 0.045 0.049 0.053
e0.65BSC 0.026BSC
e11.20 1.30 1.40 0.047 0.051 0.055
L0.10 0.20 0.30 0.004 0.008 0.012
7_Nom 7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
— VISHAY DI:- J DIZJJE}L LILILI Top View FIGURE 1. FA Documem Numbev 71334 1202:2703
AN815
Vishay Siliconix
Document Number: 71334
12-Dec-03
www.vishay.com
1
Single-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
The new single 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the single-channel version.
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the basic
pad layout and dimensions. These pad patterns are sufficient
for the low to medium power applications for which this
package is intended. Increasing the drain pad pattern yields a
reduction in thermal resistance and is a preferred footprint.
The availability of four drain leads rather than the traditional
single drain lead allows a better thermal path from the package
to the PCB and external environment.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1
identification.The pin-out of this device allows the use of four
pins as drain leads, which helps to reduce on-resistance and
junction-to-ambient thermal resistance.
FIGURE 1.
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
D
D
G
D
D
S
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
EVALUATION BOARDS  SINGLE SC70-6
The evaluation board (EVB) measures 0.6 inches by
0.5 inches. The copper pad traces are the same as in Figure 2.
The board allows examination from the outer pins to 6-pin DIP
connections, permitting test sockets to be used in evaluation
testing. See Figure 3.
FIGURE 2. SC-70 (6 leads) Single
52 (mil)
96 (mil)
13 (mil)
71 (mil)
0, 0 (mil)
18 (mil)
16 (mil)
26 (mil)
26 (mil)
654
321
The thermal performance of the single 6-pin SC-70 has been
measured on the EVB, comparing both the copper and
Alloy 42 leadframes. This test was first conducted on the
traditional Alloy 42 leadframe and was then repeated using the
1-inch2 PCB with dual-side copper coating.
— VISHAY SC70-6 SINGLE Uishau Silicunix O I c O O Q C O HO RU 150Ci25C 15007600 124°C/W 124“C/W 1) Mwmum recommended pad panem an 2) mausuy s|andavd 17mm PCB wnh R0 150 c , 25 c 212°C/W R0 150C7256 212°C/W
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Document Number: 71334
12-Dec-03
FIGURE 3.
Front of Board SC70-6 Back of Board SC70-6
vishay.com
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(Package Performance)
The junction to foot thermal resistance is a useful method of
comparing different packages thermal performance.
A helpful way of presenting the thermal performance of the
6-Pin SC-70 copper leadframe device is to compare it to the
traditional Alloy 42 version.
Thermal performance for the 6-pin SC-70 measured as
junction-to-foot thermal resistance, where the “foot” is the
drain lead of the device at the bottom where it meets the PCB.
The junction-to-foot thermal resistance is typically 40_C/W in
the copper leadframe and 163_C/W in the Alloy 42 leadframe
— a four-fold improvement. This improved performance is
obtained by the enhanced thermal conductivity of copper over
Alloy 42.
Power Dissipation
The typical RqJA for the single 6-pin SC-70 with copper
leadframe is 103_C/W steady-state, compared with 212_C/W
for the Alloy 42 version. The figures are based on the 1-inch2
FR4 test board. The following example shows how the thermal
resistance impacts power dissipation for the two different
leadframes at varying ambient temperatures.
ALLOY 42 LEADFRAME
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
212oCńW
PD+590 mW
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
212oCńW
PD+425 mW
COOPER LEADFRAME
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
124oCńW
PD+1.01 W
PD+TJ(max) *TA
RqJA
PD+150oC*60oC
124oCńW
PD+726 mW
As can be seen from the calculations above, the compact 6-pin
SC-70 copper leadframe LITTLE FOOT power MOSFET can
handle up to 1 W under the stated conditions.
Testing
To further aid comparison of copper and Alloy 42 leadframes,
Figure 5 illustrates single-channel 6-pin SC-70 thermal
performance on two different board sizes and two different pad
patterns. The measured steady-state values of RqJA for the
two leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Alloy 42 Copper
1) Minimum recommended pad pattern on
the EVB board V (see Figure 3. 329.7_C/W 208.5_C/W
2) Industry standard 1-inch2 PCB with
maximum copper both sides. 211.8_C/W 103.5_C/W
The results indicate that designers can reduce thermal
resistance (RqJA) by 36% simply by using the copper
leadframe device rather than the Alloy 42 version. In this
example, a 121_C/W reduction was achieved without an
increase in board area. If increasing in board size is feasible,
a further 105_C/W reduction could be obtained by utilizing a
1-inch2 square PCB area.
The copper leadframe versions have the following suffix:
Single: Si14xxEDH
Dual: Si19xxEDH
Complementary: Si15xxEDH
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Document Number: 71334
12-Dec-03
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3
Time (Secs)
FIGURE 4. Leadframe Comparison on EVB
Thermal Resistance (C/W)
0
1
400
80
160
100 1000
240
1010-1
10-2
10-3
10-4
10-5
Alloy
42
320
Time (Secs)
FIGURE 5. Leadframe Comparison on Alloy 42 1-inch2 PCB
Thermal Resistance (C/W)
0
1
250
50
100
100 1000
150
1010-1
10-2
10-3
10-4
10-5
200
Copper
Copper
Alloy
42
Application Note 826 VlSI-MY Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead n 057 (1 702) a use 12 438) Recommended Mwmmum Pads Dwmensmns m Inches/(mm) Documem Number 72502 «may com Rev 5m 2w rJaurOB
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72602
18 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.096
(2.438)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.067
(1.702)
0.026
(0.648)
0.045
(1.143)
0.016
(0.406)
0.026
(0.648)
0.010
(0.241)
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Revision: 08-Feb-17 1Document Number: 91000
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