Shown here is the maximum frequencies for each of the subsystems. The maximum Control subsystem clock is 150 MHz, it is also equal to the PLL system clock. The maximum for the M3 Master subsystem clock is 100 MHz, and the maximum for the ADC clock is 37.5 MHz. The last two columns in this table show the possible ADC and EPI performance at the maximum frequencies. The ADC rate is in mega samples per second and is calculated as the ADC clock divided by 13 or, in this case, 2.885 mega samples per second. Recall that there are up to two ADCs on an F28M35x device. The EPI (external peripheral interface) is limited to one-half of the Master subsystem clock, or a maximum of 50 MHz. The bottom table will show different device configurations. First, is the maximum C28x frequency system. To do this, assume that the C28x is clocked at the maximum 150 MHz, this frequency is also equal to the PLL system clock frequency. The M3 and the analog clock will be divided down from the 150 MHz. Configure the M3 clock and setting the Master subsystem clock equal to the PLL system clock. This configuration exceeds the maximum of a 100 MHz, so this option is not valid. When divided by two, this results in a 75 MHz clock, which is fine since it is less than the maximum. To clock the M3, divide by four, which results in a 37.5 MHz clock. Configure the ADC clock equal to the PLL system clock, this option exceeds the maximum ADC clock, which is 37.5 MHz, so this option is not valid. Likewise, if divided by two, the ADC clock still exceeds the maximum. Try to divide by four, this yields ADC clock of 37.5 MHz, which is equal to the ADC maximum. Choose to divide the clock by eight and clock the ADC at 18.75 MHz. The next configuration is an example of a maximum M3 frequency system. The M3 maximum is 100 MHz, the PLL system clock and the C28x subsystem clock can be also 100 MHz. The analog subsystem clock can be divided by four which yields 25 MHz, or can choose to use the divide by eight operation. The last configuration is a low end device. The C28x and the M3 are running at 60 MHz. The analog subsystem could be a divide by two, which would yield a 30 MHz ADC clock. It could also be decided to run the ADC clock at divide by four if so desired. The next slide will go into more detail on the M3 Master subsystem clocking.