The M3 subsystem clock is the main clock for the Master subsystem. The maximum for this clock is 100 MHz and it is divided down from the PLL system clock. This clock is used by the M3 CPU in most of the M3-related peripherals such as the UART, EMAC, GPIO, I2C, and general purpose timers. Other peripherals in the Master subsystem are clocked as follows: Watchdog timer one is clocked from a different clock domain OSCCLK, this clock comes from the X1 X2 pins. Having a separate clock domain for the Watchdog can be an important safety consideration. The system PLL can support a spread spectrum mode. The CAN module, however, is very susceptible to clock jitter at higher bit rates. If the application uses a spread spectrum system clock, the user can select an alternative more accurate and stable bit clock and not compromise communications. This clock can be fed in from the GPIO XCLKIN pin which is muxed on GPIO 63. The USB on this device has its own PLL. This decouples it from all of the system clock ratios used by the rest of the system. This PLL can supply the 60 MHz required by the peripheral and allows the USB to be clocked independently. Note that if GPIO clock is used by the USB directly, it is limited to 60 MHz. The GPIO XCLKIN pin can only be used in the two cases shown here—to clock the CAN and/or the USB. Finally, the clocks to the peripherals can be disabled to conserve power when the modules are not in use or when in low power modes. There are controls for clock gating in run, sleep and deep sleep modes. On the next slide, this presentation will provide a more detailed discussion of the Control subsystem clocking.